diff -urN android_2.6.29_org/arch/arm/Kconfig android_2.6.29/arch/arm/Kconfig
--- android_2.6.29_org/arch/arm/Kconfig	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -1086,7 +1086,8 @@
 
 menu "CPU Power Management"
 
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || \
+    ARCH_S3C64XX)
 
 source "drivers/cpufreq/Kconfig"
 
@@ -1126,6 +1127,10 @@
 	default y
 	select CPU_FREQ_DEFAULT_GOV_USERSPACE
 
+config CPU_FREQ_S3C64XX
+	bool "CPUfreq support for S3C64xx CPUs"
+	depends on CPU_FREQ && CPU_S3C6410
+
 endif
 
 source "drivers/cpuidle/Kconfig"
diff -urN android_2.6.29_org/arch/arm/boot/Makefile android_2.6.29/arch/arm/boot/Makefile
--- android_2.6.29_org/arch/arm/boot/Makefile	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/boot/Makefile	2009-04-10 11:13:25.000000000 +0900
@@ -73,6 +73,7 @@
 $(obj)/uImage:	$(obj)/zImage FORCE
 	$(call if_changed,uimage)
 	@echo '  Image $@ is ready'
+	cp -f $(obj)/uImage /tftpboot/uImage2628_6410
 
 $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
 	$(Q)$(MAKE) $(build)=$(obj)/bootp $@
diff -urN android_2.6.29_org/arch/arm/configs/nead6410_android_defconfig android_2.6.29/arch/arm/configs/nead6410_android_defconfig
--- android_2.6.29_org/arch/arm/configs/nead6410_android_defconfig	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/configs/nead6410_android_defconfig	2009-04-20 13:34:30.000000000 +0900
@@ -0,0 +1,1347 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29
+# Mon Apr 20 12:00:32 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ASHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+CONFIG_ARCH_S3C64XX=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_PLAT_S3C64XX=y
+CONFIG_CPU_S3C6400_INIT=y
+CONFIG_CPU_S3C6400_CLOCK=y
+CONFIG_S3C64XX_DMA=y
+CONFIG_S3C64XX_SETUP_I2C0=y
+CONFIG_S3C64XX_SETUP_I2C1=y
+CONFIG_S3C64XX_SETUP_FB_24BPP=y
+CONFIG_S3C64XX_SETUP_USBOTG=y
+CONFIG_PLAT_S3C=y
+
+#
+# Boot options
+#
+CONFIG_S3C_BOOT_ERROR_RESET=y
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C_PM_DEBUG_LED_SMDK is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_S3C_GPIO_CFG_S3C24XX=y
+CONFIG_S3C_GPIO_CFG_S3C64XX=y
+CONFIG_S3C_DMA=y
+CONFIG_S3C_DEV_HSMMC=y
+CONFIG_S3C_DEV_HSMMC1=y
+CONFIG_S3C_DEV_I2C1=y
+CONFIG_S3C_DEV_FB=y
+CONFIG_S3C_DEV_USB_HOST=y
+CONFIG_CPU_S3C6410=y
+CONFIG_S3C6410_SETUP_SDHCI=y
+CONFIG_MACH_SMDK6410=y
+# CONFIG_SMDK6410_SD_CH0 is not set
+CONFIG_SMDK6410_SD_CH1=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_VIC=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_UNEVICTABLE_LRU is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/nfs rw nfsroot=12.23.106.52:/opt/small_root_eabi ip=192.168.0.20:12.23.106.52:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200 mem=128M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+CONFIG_NFTL=y
+# CONFIG_NFTL_RW is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_S3C=y
+# CONFIG_MTD_NAND_S3C_DEBUG is not set
+CONFIG_MTD_NAND_S3C_HWECC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+CONFIG_UID_STAT=y
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+CONFIG_TOUCHSCREEN_S3C=y
+CONFIG_TOUCHSCREEN_NEW=y
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=4
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C6400=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DCC_TTY=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_PCA963X is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C=y
+CONFIG_FB_S3C_DEBUG_REGWRITE=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_S3C24XX_SOC=y
+CONFIG_SND_S3C_I2SV2_SOC=y
+CONFIG_SND_S3C64XX_SOC_I2S=y
+# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
+# CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X is not set
+CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8960=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8960=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_COMPAT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+# CONFIG_MMC_PARANOID_SD_INIT is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_MMC_BLOCK_PARANOID_RESUME=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+CONFIG_SWITCH_GPIO=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_MEILHAUS is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+# CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION is not set
+# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_SOLARIS_X86_PARTITION=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_S3C_UART=1
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff -urN android_2.6.29_org/arch/arm/configs/nead6410_defconfig android_2.6.29/arch/arm/configs/nead6410_defconfig
--- android_2.6.29_org/arch/arm/configs/nead6410_defconfig	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/configs/nead6410_defconfig	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,1239 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29
+# Thu Apr  2 15:35:48 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+CONFIG_ARCH_S3C64XX=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_PLAT_S3C64XX=y
+CONFIG_CPU_S3C6400_INIT=y
+CONFIG_CPU_S3C6400_CLOCK=y
+CONFIG_S3C64XX_DMA=y
+CONFIG_S3C64XX_SETUP_I2C0=y
+CONFIG_S3C64XX_SETUP_I2C1=y
+CONFIG_S3C64XX_SETUP_FB_24BPP=y
+CONFIG_S3C64XX_SETUP_USBOTG=y
+CONFIG_PLAT_S3C=y
+
+#
+# Boot options
+#
+CONFIG_S3C_BOOT_ERROR_RESET=y
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_S3C_GPIO_CFG_S3C24XX=y
+CONFIG_S3C_GPIO_CFG_S3C64XX=y
+CONFIG_S3C_DMA=y
+CONFIG_S3C_DEV_HSMMC=y
+CONFIG_S3C_DEV_HSMMC1=y
+CONFIG_S3C_DEV_I2C1=y
+CONFIG_S3C_DEV_FB=y
+CONFIG_S3C_DEV_USB_HOST=y
+CONFIG_CPU_S3C6410=y
+CONFIG_S3C6410_SETUP_SDHCI=y
+CONFIG_MACH_SMDK6410=y
+CONFIG_SMDK6410_SD_CH0=y
+# CONFIG_SMDK6410_SD_CH1 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_VIC=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/nfs rw nfsroot=12.23.106.52:/opt/small_root_eabi ip=192.168.0.20:12.23.106.52:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200 mem=128M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_CS89x0=y
+CONFIG_CS89x0_NONISA_IRQ=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+CONFIG_TOUCHSCREEN_S3C=y
+CONFIG_TOUCHSCREEN_NEW=y
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=4
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C6400=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C=y
+CONFIG_FB_S3C_DEBUG_REGWRITE=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_VERBOSE=y
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SOC=y
+CONFIG_SND_S3C24XX_SOC=y
+CONFIG_SND_S3C_I2SV2_SOC=y
+CONFIG_SND_S3C64XX_SOC_I2S=y
+# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
+# CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X is not set
+CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8960=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8960=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_COMPAT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_S3C is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_SOLARIS_X86_PARTITION=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=1
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff -urN android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/dma.h android_2.6.29/arch/arm/mach-s3c6400/include/mach/dma.h
--- android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/dma.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6400/include/mach/dma.h	2009-04-10 11:13:25.000000000 +0900
@@ -11,6 +11,63 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
 
-/* currently nothing here, placeholder */
+#define S3C_DMA_CHANNELS	(16)
+
+/* see mach-s3c2410/dma.h for notes on dma channel numbers */
+
+/* Note, for the S3C64XX architecture we keep the DMACH_
+ * defines in the order they are allocated to [S]DMA0/[S]DMA1
+ * so that is easy to do DHACH_ -> DMA controller conversion
+ */ 
+enum dma_ch {
+	/* DMA0/SDMA0 */
+	DMACH_UART0 = 0,
+	DMACH_UART0_SRC2,
+	DMACH_UART1,
+	DMACH_UART1_SRC2,
+	DMACH_UART2,
+	DMACH_UART2_SRC2,
+	DMACH_UART3,
+	DMACH_UART3_SRC2,
+	DMACH_PCM0_TX,
+	DMACH_PCM0_RX,
+	DMACH_I2S0_OUT,
+	DMACH_I2S0_IN,
+	DMACH_SPI0_TX,
+	DMACH_SPI0_RX,
+	DMACH_HSI_I2SV40_TX,
+	DMACH_HSI_I2SV40_RX,
+
+	/* DMA1/SDMA1 */
+	DMACH_PCM1_TX = 16,
+	DMACH_PCM1_RX,
+	DMACH_I2S1_OUT,
+	DMACH_I2S1_IN,
+	DMACH_SPI1_TX,
+	DMACH_SPI1_RX,
+	DMACH_AC97_PCMOUT,
+	DMACH_AC97_PCMIN,
+	DMACH_AC97_MICIN,
+	DMACH_PWM, 
+	DMACH_IRDA,
+	DMACH_EXTERNAL,
+	DMACH_RES1,
+	DMACH_RES2,
+	DMACH_SECURITY_RX,	/* SDMA1 only */
+	DMACH_SECURITY_TX,	/* SDMA1 only */
+	DMACH_MAX		/* the end */
+};
+
+static __inline__ int s3c_dma_has_circular(void)
+{
+	/* we will be supporting ciruclar buffers as soon as we have DMA
+	 * engine support.
+	 */
+	return 1;
+}
+
+#define S3C2410_DMAF_CIRCULAR		(1 << 0)
+
+#include <plat/dma.h>
 
 #endif /* __ASM_ARCH_IRQ_H */
diff -urN android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/map.h android_2.6.29/arch/arm/mach-s3c6400/include/mach/map.h
--- android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/map.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6400/include/mach/map.h	2009-04-16 20:17:23.000000000 +0900
@@ -40,21 +40,47 @@
 
 #define S3C64XX_PA_FB		(0x77100000)
 #define S3C64XX_PA_SYSCON	(0x7E00F000)
+#define S3C64XX_PA_IIS0		(0x7F002000)
+#define S3C64XX_PA_IIS1		(0x7F003000)
 #define S3C64XX_PA_TIMER	(0x7F006000)
 #define S3C64XX_PA_IIC0		(0x7F004000)
+#define S3C64XX_PA_IIS_V40      (0x7F00D000)
 #define S3C64XX_PA_IIC1		(0x7F00F000)
 
 #define S3C64XX_PA_GPIO		(0x7F008000)
-#define S3C64XX_VA_GPIO		S3C_ADDR(0x00500000)
+#define S3C64XX_VA_GPIO		S3C_VA_GPIO
 #define S3C64XX_SZ_GPIO		SZ_4K
 
 #define S3C64XX_PA_SDRAM	(0x50000000)
+#define S3C64XX_PA_TZIC0	(0x71000000)
+#define S3C64XX_PA_TZIC1	(0x71100000)
 #define S3C64XX_PA_VIC0		(0x71200000)
 #define S3C64XX_PA_VIC1		(0x71300000)
 
+#define S3C64XX_PA_MODEM	(0x74108000)
+#define S3C64XX_VA_MODEM	S3C_ADDR(0x00600000)
+
+#define S3C64XX_PA_USBHOST	(0x74300000)
+
+#define S3C64XX_PA_ADC	(0x7E00B000)
 /* place VICs close together */
 #define S3C_VA_VIC0		(S3C_VA_IRQ + 0x00)
 #define S3C_VA_VIC1		(S3C_VA_IRQ + 0x10000)
+#define S3C_VA_TZIC0		(S3C_VA_IRQ + 0x20000)
+#define S3C_VA_TZIC1		(S3C_VA_IRQ + 0x30000)
+
+/* Host I/F Indirect & Direct */
+#define S3C64XX_VA_HOSTIFA	S3C_VA_HOSTIFA
+#define S3C64XX_PA_HOSTIFA	(0x74000000)
+#define S3C64XX_SZ_HOSTIFA	SZ_1M
+
+#define S3C64XX_VA_HOSTIFB	S3C_VA_HOSTIFB
+#define S3C64XX_PA_HOSTIFB	(0x74100000)
+#define S3C64XX_SZ_HOSTIFB	SZ_1M
+
+/* NAND flash controller */
+#define S3C64XX_PA_NAND	   	(0x70200000)
+#define S3C64XX_SZ_NAND	   	SZ_1M
 
 /* compatibiltiy defines. */
 #define S3C_PA_TIMER		S3C64XX_PA_TIMER
@@ -64,5 +90,23 @@
 #define S3C_PA_IIC		S3C64XX_PA_IIC0
 #define S3C_PA_IIC1		S3C64XX_PA_IIC1
 #define S3C_PA_FB		S3C64XX_PA_FB
+#define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
+
+#define S3C_PA_ADC		S3C64XX_PA_ADC
+#define S3C_PA_IIS		S3C64XX_PA_IIS0
+#define S3C_SZ_IIS		SZ_8K
+
+#define S3C64XX_VA_OTG		S3C_VA_OTG
+#define S3C64XX_PA_OTG		(0x7C000000)
+
+#define S3C64XX_VA_OTGSFR	S3C_VA_OTGSFR
+#define S3C64XX_PA_OTGSFR	(0x7C100000)
+
+#define S3C64XX_VA_CS89X0	S3C_VA_CS89X0
+#define S3C64XX_PA_CS89X0	(0x30000000)
+#define S3C64XX_SZ_CS89X0	SZ_1M
 
+#define S3C64XX_VA_SMSC9220	S3C_VA_SMSC9220
+#define S3C64XX_PA_SMSC9220	(0x30000000)
+#define S3C64XX_SZ_SMSC9220	SZ_1M
 #endif /* __ASM_ARCH_6400_MAP_H */
diff -urN android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/regs-clock.h android_2.6.29/arch/arm/mach-s3c6400/include/mach/regs-clock.h
--- android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/regs-clock.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6400/include/mach/regs-clock.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	http://armlinux.simtec.co.uk/
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - clock register compatibility with s3c24xx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/regs-clock.h>
+
diff -urN android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/system.h android_2.6.29/arch/arm/mach-s3c6400/include/mach/system.h
--- android_2.6.29_org/arch/arm/mach-s3c6400/include/mach/system.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6400/include/mach/system.h	2009-04-10 11:13:25.000000000 +0900
@@ -11,9 +11,29 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
 
+#include <linux/io.h>
+#include <mach/map.h>
+
+#include <plat/regs-sys.h>
+#include <plat/regs-syscon-power.h>
+
 static void arch_idle(void)
 {
-	/* nothing here yet */
+	unsigned long flags;
+	u32 mode;
+
+	/* ensure that if we execute the cpu idle sequence that we
+	 * go into idle mode instead of powering off. */
+
+	local_irq_save(flags);
+	mode = __raw_readl(S3C64XX_PWR_CFG);
+	mode &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+	mode |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
+	__raw_writel(mode, S3C64XX_PWR_CFG);
+
+	local_irq_restore(flags);
+
+	cpu_do_idle();
 }
 
 static void arch_reset(char mode)
diff -urN android_2.6.29_org/arch/arm/mach-s3c6410/Kconfig android_2.6.29/arch/arm/mach-s3c6410/Kconfig
--- android_2.6.29_org/arch/arm/mach-s3c6410/Kconfig	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6410/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -26,6 +26,7 @@
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_I2C1
 	select S3C_DEV_FB
+        select S3C_DEV_USB_HOST
 	select S3C6410_SETUP_SDHCI
 	select S3C64XX_SETUP_I2C1
 	select S3C64XX_SETUP_FB_24BPP
diff -urN android_2.6.29_org/arch/arm/mach-s3c6410/\ android_2.6.29/arch/arm/mach-s3c6410/\
--- android_2.6.29_org/arch/arm/mach-s3c6410/\	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6410/\	2009-04-17 19:11:38.000000000 +0900
@@ -0,0 +1,352 @@
+/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <video/platform_lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-modem.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-sys.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/pm.h>
+#include <plat/ts.h>
+#include <plat/adc.h>
+
+#include <plat/nand.h>
+#include <plat/partition.h>
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hs-otg.h>
+
+#include <plat/gpio-bank-n.h>
+
+#include <linux/smsc911x.h>
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[2] = {
+		.hwport      = 2,
+		.flags       = 0,
+		.ucon        = 0x3c5,
+		.ulcon       = 0x03,
+		.ufcon       = 0x51,
+	},
+	[3] = {
+		.hwport      = 3,
+		.flags       = 0,
+		.ucon        = 0x3c5,
+		.ulcon       = 0x03,
+		.ufcon       = 0x51,
+	},
+};
+
+/* framebuffer and LCD setup. */
+
+/* GPF15 = LCD backlight control
+ * GPF13 => Panel power
+ * GPN5 = LCD nRESET signal
+ * PWM_TOUT1 => backlight brightness
+ */
+
+static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power) {
+		gpio_direction_output(S3C64XX_GPN(9), 1);
+		gpio_direction_output(S3C64XX_GPF(15), 1);
+
+		/* fire nRESET on power up */
+/*		
+		gpio_direction_output(S3C64XX_GPN(5), 0);
+		msleep(10);
+		gpio_direction_output(S3C64XX_GPN(5), 1);
+		msleep(1);
+*/		
+	} else {
+		gpio_direction_output(S3C64XX_GPN(9), 0);
+		gpio_direction_output(S3C64XX_GPF(15), 0);
+	}
+}
+
+static struct plat_lcd_data smdk6410_lcd_power_data = {
+	.set_power	= smdk6410_lcd_power_set,
+};
+
+static struct platform_device smdk6410_lcd_powerdev = {
+	.name			= "platform-lcd",
+	.dev.parent		= &s3c_device_fb.dev,
+	.dev.platform_data	= &smdk6410_lcd_power_data,
+};
+
+static struct s3c_fb_pd_win smdk6410_fb_win0 = {
+	/* this is to ensure we use win0 */
+	.win_mode	= {
+		.pixclock	= 40816,
+		.left_margin	= 100,
+		.right_margin	= 28,
+		.upper_margin	= 13,
+		.lower_margin	= 30,
+		.hsync_len	= 8,
+		.vsync_len	= 2,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.max_bpp	= 32,
+	.default_bpp	= 16,
+};
+
+/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
+static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
+	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.win[0]		= &smdk6410_fb_win0,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_BGR,
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | VIDCON1_INV_VCLK,
+};
+
+/* CS8900 */
+static struct resource smdk6410_cs89x0_resources[] = {
+        [0] = {
+                .start  = S3C64XX_PA_CS89X0,
+                .end    = S3C64XX_PA_CS89X0 + SZ_1M,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_EINT(11),
+                .end    = IRQ_EINT(11),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device s3c_device_cs89x0 = {
+	.name           = "cirrus-cs89x0",
+	.id             =  -1,
+	.num_resources  = ARRAY_SIZE(smdk6410_cs89x0_resources),
+	.resource       = smdk6410_cs89x0_resources,
+};
+
+#if 0
+static struct map_desc smdk6410_iodesc[] = {
+        IODESC_ENT(CS89X0),
+};
+#else
+static struct map_desc smdk6410_iodesc[] = {
+        IODESC_ENT(SMSC9220),
+};
+#endif
+
+static struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags = SMSC911X_USE_32BIT,
+	.phy_interface = PHY_INTERFACE_MODE_MII,
+};
+
+static struct resource s3c_smsc911x_resources[] = {
+      [0] = {
+              .start  = S3C64XX_PA_SMSC9220,
+              .end    = S3C64XX_PA_SMSC9220 + SZ_1M,
+              .flags  = IORESOURCE_MEM,
+      },
+      [1] = {
+              .start = IRQ_EINT(11),
+              .end   = IRQ_EINT(11),
+              .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_smsc911x = {
+      .name           = "smsc911x",
+      .id             =  -1,
+      .num_resources  = ARRAY_SIZE(s3c_smsc911x_resources),
+      .resource       = s3c_smsc911x_resources,
+      .dev = {
+              .platform_data = &smsc911x_config,
+      },
+};
+
+struct platform_device s3c24xx_pwm_device = {
+	.name 		= "s3c24xx_pwm",
+	.num_resources	= 0,
+};
+
+static struct platform_device *smdk6410_devices[] __initdata = {
+#ifdef CONFIG_SMDK6410_SD_CH0
+	&s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_SMDK6410_SD_CH1
+	&s3c_device_hsmmc1,
+#endif
+	&s3c_device_ts,
+	&s3c_device_adc,
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+	&s3c_device_fb,
+	&s3c_device_nand,
+	&s3c_device_usb,
+	&smdk6410_lcd_powerdev,
+	&s3c_device_usbgadget,
+	&s3c24xx_pwm_device,
+	//&s3c_device_cs89x0
+	&s3c_device_smsc911x
+};
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+//	{ I2C_BOARD_INFO("24c08", 0x50), },
+	{ I2C_BOARD_INFO("wm8960", 0x1a), },
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+//	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
+};
+
+static struct s3c_ts_mach_info s3c_ts_platform __initdata = {
+                .delay 			= 10000,
+                .presc 			= 49,
+                .oversampling_shift	= 2,
+		.resol_bit 		= 12,
+		.s3c_adc_con		= ADC_TYPE_2,
+};
+
+static struct s3c_adc_mach_info s3c_adc_platform __initdata = {
+	/* s3c6410 support 12-bit resolution */
+	.delay		= 10000,
+	.presc 		= 49,
+	.resolution 	= 12,
+};
+
+static void __init smdk6410_map_io(void)
+{
+	u32 tmp;
+
+	s3c_device_nand.name = "s3c6410-nand";
+	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
+	s3c24xx_init_clocks(12000000);
+	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+	/* set the LCD type */
+
+	tmp = __raw_readl(S3C64XX_SPCON);
+	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+	__raw_writel(tmp, S3C64XX_SPCON);
+
+	/* remove the lcd bypass */
+	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+	tmp &= ~MIFPCON_LCD_BYPASS;
+	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+struct s3c_plat_otg_data s3c_hs_otg_plat_data = {
+	.phyclk = REF_CLK_OSCC
+};
+
+static void s3c_wifi_setting(void)
+{
+	unsigned int tmp;
+
+        //GPL11, wifi enable 
+        tmp = __raw_readl(S3C64XX_GPLBASE + 0x04);
+        tmp &= ~(0xf <<12);
+        tmp |= (0x1 << 12);
+        __raw_writel(tmp, S3C64XX_GPLBASE + 0x04);
+
+        //GPL12, wifi reset 
+        tmp = __raw_readl(S3C64XX_GPLBASE + 0x04);
+        tmp &= ~(0x3 <<22);
+        tmp &= ~(0x3 <<16);
+        tmp |= (2 << 22);
+
+        //GPN8 LAN_SLEEP high
+        tmp = __raw_readl(S3C64XX_GPNDAT);
+        __raw_writel(tmp |= (1<<8) , S3C64XX_GPNDAT);
+}
+
+static void __init smdk6410_machine_init(void)
+{
+	unsigned int tmp;
+
+	s3c_device_nand.dev.platform_data = &s3c_nand_mtd_part_info;
+	s3c_device_usbgadget.dev.platform_data = &s3c_hs_otg_plat_data;
+	s3c_i2c0_set_platdata(NULL);
+	s3c_i2c1_set_platdata(NULL);
+	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	s3c_ts_set_platdata(&s3c_ts_platform);
+	s3c_adc_set_platdata(&s3c_adc_platform);
+
+	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
+
+	s3c_wifi_setting();
+}
+
+MACHINE_START(SMDK6410, "SMDK6410")
+	/* Maintainer: Ben Dooks <ben@fluff.org> */
+	.phys_io	= S3C_PA_UART & 0xfff00000,
+	.io_pg_offst	= (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+	.boot_params	= S3C64XX_PA_SDRAM + 0x100,
+
+	.init_irq	= s3c6410_init_irq,
+	.map_io		= smdk6410_map_io,
+	.init_machine	= smdk6410_machine_init,
+	.timer		= &s3c24xx_timer,
+MACHINE_END
diff -urN android_2.6.29_org/arch/arm/mach-s3c6410/mach-smdk6410.c android_2.6.29/arch/arm/mach-s3c6410/mach-smdk6410.c
--- android_2.6.29_org/arch/arm/mach-s3c6410/mach-smdk6410.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6410/mach-smdk6410.c	2009-04-17 19:34:18.000000000 +0900
@@ -24,6 +24,10 @@
 #include <linux/fb.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
 
 #include <video/platform_lcd.h>
 
@@ -39,13 +43,26 @@
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-modem.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-sys.h>
 #include <plat/iic.h>
 #include <plat/fb.h>
+#include <plat/pm.h>
+#include <plat/ts.h>
+#include <plat/adc.h>
 
+#include <plat/nand.h>
+#include <plat/partition.h>
 #include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/regs-usb-hs-otg.h>
+
+#include <plat/gpio-bank-n.h>
+
+#include <linux/smsc911x.h>
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -66,6 +83,20 @@
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
+	[2] = {
+		.hwport      = 2,
+		.flags       = 0,
+		.ucon        = 0x3c5,
+		.ulcon       = 0x03,
+		.ufcon       = 0x51,
+	},
+	[3] = {
+		.hwport      = 3,
+		.flags       = 0,
+		.ucon        = 0x3c5,
+		.ulcon       = 0x03,
+		.ufcon       = 0x51,
+	},
 };
 
 /* framebuffer and LCD setup. */
@@ -80,17 +111,19 @@
 				   unsigned int power)
 {
 	if (power) {
-		gpio_direction_output(S3C64XX_GPF(13), 1);
+		gpio_direction_output(S3C64XX_GPN(9), 1);
 		gpio_direction_output(S3C64XX_GPF(15), 1);
 
 		/* fire nRESET on power up */
+/*		
 		gpio_direction_output(S3C64XX_GPN(5), 0);
 		msleep(10);
 		gpio_direction_output(S3C64XX_GPN(5), 1);
 		msleep(1);
+*/		
 	} else {
+		gpio_direction_output(S3C64XX_GPN(9), 0);
 		gpio_direction_output(S3C64XX_GPF(15), 0);
-		gpio_direction_output(S3C64XX_GPF(13), 0);
 	}
 }
 
@@ -107,13 +140,13 @@
 static struct s3c_fb_pd_win smdk6410_fb_win0 = {
 	/* this is to ensure we use win0 */
 	.win_mode	= {
-		.pixclock	= 41094,
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
+		.pixclock	= 40816,
+		.left_margin	= 100,
+		.right_margin	= 28,
+		.upper_margin	= 13,
+		.lower_margin	= 30,
+		.hsync_len	= 8,
+		.vsync_len	= 2,
 		.xres		= 800,
 		.yres		= 480,
 	},
@@ -125,51 +158,205 @@
 static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
 	.win[0]		= &smdk6410_fb_win0,
-	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_BGR,
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | VIDCON1_INV_VCLK,
+};
+
+/* CS8900 */
+static struct resource smdk6410_cs89x0_resources[] = {
+        [0] = {
+                .start  = S3C64XX_PA_CS89X0,
+                .end    = S3C64XX_PA_CS89X0 + SZ_1M,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_EINT(11),
+                .end    = IRQ_EINT(11),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device s3c_device_cs89x0 = {
+	.name           = "cirrus-cs89x0",
+	.id             =  -1,
+	.num_resources  = ARRAY_SIZE(smdk6410_cs89x0_resources),
+	.resource       = smdk6410_cs89x0_resources,
+};
+
+#if 0
+static struct map_desc smdk6410_iodesc[] = {
+        IODESC_ENT(CS89X0),
+};
+#else
+static struct map_desc smdk6410_iodesc[] = {
+        IODESC_ENT(SMSC9220),
+};
+#endif
+
+static struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags = SMSC911X_USE_32BIT,
+	.phy_interface = PHY_INTERFACE_MODE_MII,
+};
+
+static struct resource s3c_smsc911x_resources[] = {
+      [0] = {
+              .start  = S3C64XX_PA_SMSC9220,
+              .end    = S3C64XX_PA_SMSC9220 + SZ_1M,
+              .flags  = IORESOURCE_MEM,
+      },
+      [1] = {
+              .start = IRQ_EINT(11),
+              .end   = IRQ_EINT(11),
+              .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_smsc911x = {
+      .name           = "smsc911x",
+      .id             =  -1,
+      .num_resources  = ARRAY_SIZE(s3c_smsc911x_resources),
+      .resource       = s3c_smsc911x_resources,
+      .dev = {
+              .platform_data = &smsc911x_config,
+      },
 };
 
-static struct map_desc smdk6410_iodesc[] = {};
+struct platform_device s3c24xx_pwm_device = {
+	.name 		= "s3c24xx_pwm",
+	.num_resources	= 0,
+};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
-#ifdef CONFIG_SMDK6410_SD_CH0
+//#ifdef CONFIG_SMDK6410_SD_CH0
 	&s3c_device_hsmmc0,
-#endif
+//#endif
 #ifdef CONFIG_SMDK6410_SD_CH1
 	&s3c_device_hsmmc1,
 #endif
+	&s3c_device_ts,
+	&s3c_device_adc,
 	&s3c_device_i2c0,
 	&s3c_device_i2c1,
 	&s3c_device_fb,
+	&s3c_device_nand,
+	&s3c_device_usb,
 	&smdk6410_lcd_powerdev,
+	&s3c_device_usbgadget,
+	&s3c24xx_pwm_device,
+	//&s3c_device_cs89x0
+	&s3c_device_smsc911x
 };
 
 static struct i2c_board_info i2c_devs0[] __initdata = {
-	{ I2C_BOARD_INFO("24c08", 0x50), },
-	{ I2C_BOARD_INFO("wm8580", 0x1b), },
+//	{ I2C_BOARD_INFO("24c08", 0x50), },
+	{ I2C_BOARD_INFO("wm8960", 0x1a), },
 };
 
 static struct i2c_board_info i2c_devs1[] __initdata = {
-	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
+//	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
+};
+
+static struct s3c_ts_mach_info s3c_ts_platform __initdata = {
+                .delay 			= 10000,
+                .presc 			= 49,
+                .oversampling_shift	= 2,
+		.resol_bit 		= 12,
+		.s3c_adc_con		= ADC_TYPE_2,
+};
+
+static struct s3c_adc_mach_info s3c_adc_platform __initdata = {
+	/* s3c6410 support 12-bit resolution */
+	.delay		= 10000,
+	.presc 		= 49,
+	.resolution 	= 12,
 };
 
 static void __init smdk6410_map_io(void)
 {
+	u32 tmp;
+
+	s3c_device_nand.name = "s3c6410-nand";
 	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
 	s3c24xx_init_clocks(12000000);
 	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+	/* set the LCD type */
+
+	tmp = __raw_readl(S3C64XX_SPCON);
+	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+	__raw_writel(tmp, S3C64XX_SPCON);
+
+	/* remove the lcd bypass */
+	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+	tmp &= ~MIFPCON_LCD_BYPASS;
+	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+struct s3c_plat_otg_data s3c_hs_otg_plat_data = {
+	.phyclk = REF_CLK_OSCC
+};
+
+static void s3c_wifi_setting(void)
+{
+	unsigned int tmp;
+
+        //GPL11, wifi enable 
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x04);
+        tmp &= ~(0xf <<12);
+        tmp |= (0x1 << 12);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x04);
+
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x08);
+        tmp &= ~(0x3 <<22);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x08);
+
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x0C);
+        tmp &= ~(0x1 <<11);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x0C);
+
+        //GPL12, wifi reset 
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x04);
+        tmp &= ~(0xf <<16);
+        tmp |= (0x1 << 16);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x04);
+
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x08);
+        tmp &= ~(0x3 <<24);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x08);
+
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x0C);
+        tmp |= (0x1 <<12);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x0C);
+
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x0C);
+        tmp &= ~(0x1 <<12);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x0C);
+
+        tmp = __raw_readl(S3C64XX_GPL_BASE + 0x0C);
+        tmp |= (0x1 <<12);
+        __raw_writel(tmp, S3C64XX_GPL_BASE + 0x0C);
 }
 
 static void __init smdk6410_machine_init(void)
 {
+	unsigned int tmp;
+
+	s3c_device_nand.dev.platform_data = &s3c_nand_mtd_part_info;
+	s3c_device_usbgadget.dev.platform_data = &s3c_hs_otg_plat_data;
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	s3c_ts_set_platdata(&s3c_ts_platform);
+	s3c_adc_set_platdata(&s3c_adc_platform);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
 	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
+
+	s3c_wifi_setting();
 }
 
 MACHINE_START(SMDK6410, "SMDK6410")
diff -urN android_2.6.29_org/arch/arm/mach-s3c6410/setup-sdhci.c android_2.6.29/arch/arm/mach-s3c6410/setup-sdhci.c
--- android_2.6.29_org/arch/arm/mach-s3c6410/setup-sdhci.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/mach-s3c6410/setup-sdhci.c	2009-04-17 17:10:13.000000000 +0900
@@ -79,7 +79,7 @@
 	else
 		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
 
-	printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
+	//printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
 	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
 	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
 }
diff -urN android_2.6.29_org/arch/arm/plat-s3c/Kconfig android_2.6.29/arch/arm/plat-s3c/Kconfig
--- android_2.6.29_org/arch/arm/plat-s3c/Kconfig	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -71,6 +71,15 @@
 	  Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
 	  for more information.
 
+config S3C_PM_DEBUG_LED_SMDK
+       bool "SMDK LED suspend/resume debugging"
+       depends on PM && (MACH_SMDK6410)
+       help
+         Say Y here to enable the use of the SMDK LEDs on the baseboard
+	 for debugging of the state of the suspend and resume process.
+
+	 Note, this currently only works for S3C64XX based SMDK boards.
+
 config S3C2410_PM_CHECK
 	bool "S3C2410 PM Suspend Memory CRC"
 	depends on PM && CRC32
@@ -150,6 +159,18 @@
 	  Internal configuration to enable S3C64XX style GPIO configuration
 	  functions.
 
+# DMA
+
+config S3C_DMA
+	bool
+	help
+	  Internal configuration for S3C DMA core
+
+config S3C_PWM
+	bool
+	help
+	  PWM timer code for the S3C2410, and similar processors
+
 # device definitions to compile in
 
 config S3C_DEV_HSMMC
@@ -172,4 +193,14 @@
 	help
 	  Compile in platform device definition for framebuffer
 
+config S3C_DEV_USB_HOST
+	bool
+	help
+	  Compile in platform device definition for USB host.
+
+config S3C_DEV_CAMIF
+	bool
+	help
+	  Compile in platform device definitions for camera interface code
+
 endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c/Makefile android_2.6.29/arch/arm/plat-s3c/Makefile
--- android_2.6.29_org/arch/arm/plat-s3c/Makefile	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/Makefile	2009-04-10 13:13:23.000000000 +0900
@@ -18,6 +18,16 @@
 obj-y				+= gpio.o
 obj-y				+= gpio-config.o
 
+# DMA support
+
+obj-$(CONFIG_S3C_DMA)		+= dma.o
+
+# PM support
+
+obj-$(CONFIG_PM)		+= pm.o
+obj-$(CONFIG_PM)		+= pm-gpio.o
+obj-$(CONFIG_S3C2410_PM_CHECK)	+= pm-check.o
+
 # devices
 
 obj-$(CONFIG_S3C_DEV_HSMMC)	+= dev-hsmmc.o
@@ -25,3 +35,10 @@
 obj-y				+= dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)	+= dev-i2c1.o
 obj-$(CONFIG_S3C_DEV_FB)	+= dev-fb.o
+obj-$(CONFIG_S3C_DEV_USB_HOST)	+= dev-usb.o
+obj-$(CONFIG_S3C_DEV_CAMIF)	+= dev-camif.o
+obj-$(CONFIG_TOUCHSCREEN_S3C)	+= dev-ts.o
+
+obj-$(CONFIG_S3C_PWM)		+= pwm.o
+obj-$(CONFIG_S3C_DMA)		+= dma.o
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/dev-camif.c android_2.6.29/arch/arm/plat-s3c/dev-camif.c
--- android_2.6.29_org/arch/arm/plat-s3c/dev-camif.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/dev-camif.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,65 @@
+/* linux/arch/arm/plat-s3c/dev-camif.c
+ *
+ * Copyright 2009 Openmoko, Inc.
+ * Werner Almesberger <werner@openmoko.org>
+ *
+ * based on dev-hsmmc.c which is
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for camera interface devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+
+#define	S3C6400_PA_CAMIF	0x78000000
+#define S3C24XX_SZ_CAMIF	(0x1000)
+
+
+static struct resource s3c_camif_resource[] = {
+	[0] = {
+		.start = S3C6400_PA_CAMIF,
+		.end   = S3C6400_PA_CAMIF + S3C24XX_SZ_CAMIF - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_CAMIF_C,
+		.end   = IRQ_CAMIF_C,
+		.flags = IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start = IRQ_CAMIF_P,
+		.end   = IRQ_CAMIF_P,
+		.flags = IORESOURCE_IRQ,
+	}
+
+};
+
+static u64 s3c_device_camif_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_camif = {
+	.name		  = "s3c-camif",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_camif_resource),
+	.resource	  = s3c_camif_resource,
+	.dev              = {
+		.dma_mask = &s3c_device_camif_dmamask,
+		.coherent_dma_mask = 0xffffffffUL
+	}
+};
+
+EXPORT_SYMBOL(s3c_device_camif);
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/dev-hsmmc.c android_2.6.29/arch/arm/plat-s3c/dev-hsmmc.c
--- android_2.6.29_org/arch/arm/plat-s3c/dev-hsmmc.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/dev-hsmmc.c	2009-04-17 20:26:27.000000000 +0900
@@ -44,7 +44,8 @@
 };
 
 struct platform_device s3c_device_hsmmc0 = {
-	.name		= "s3c-sdhci",
+	//.name		= "s3c-sdhci",
+	.name		= "libertas_sdio",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(s3c_hsmmc_resource),
 	.resource	= s3c_hsmmc_resource,
diff -urN android_2.6.29_org/arch/arm/plat-s3c/dev-i2c0.c android_2.6.29/arch/arm/plat-s3c/dev-i2c0.c
--- android_2.6.29_org/arch/arm/plat-s3c/dev-i2c0.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/dev-i2c0.c	2009-04-10 11:13:25.000000000 +0900
@@ -52,7 +52,8 @@
 	.slave_addr	= 0x10,
 	.bus_freq	= 100*1000,
 	.max_freq	= 400*1000,
-	.sda_delay	= S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+//	.max_freq	= 100*1000,
+	.sda_delay	= S3C2410_IICLC_SDA_DELAY15 | S3C2410_IICLC_FILTER_ON,
 };
 
 void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
diff -urN android_2.6.29_org/arch/arm/plat-s3c/dev-ts.c android_2.6.29/arch/arm/plat-s3c/dev-ts.c
--- android_2.6.29_org/arch/arm/plat-s3c/dev-ts.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/dev-ts.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,65 @@
+/* linux/arch/arm/plat-s3c/dev-ts.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for hsmmc devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/irq.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/ts.h>
+
+/* Touch srcreen */
+static struct resource s3c_ts_resource[] = {
+	[0] = {
+		.start = S3C_PA_ADC,
+		.end   = S3C_PA_ADC + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_PENDN,
+		.end   = IRQ_PENDN,
+		.flags = IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start = IRQ_ADC,
+		.end   = IRQ_ADC,
+		.flags = IORESOURCE_IRQ,
+	}
+	
+};
+
+struct platform_device s3c_device_ts = {
+	.name		  = "s3c-ts",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_ts_resource),
+	.resource	  = s3c_ts_resource,
+};
+
+void __init s3c_ts_set_platdata(struct s3c_ts_mach_info *pd)
+{
+	struct s3c_ts_mach_info *npd;
+
+//	npd = kmalloc(sizeof(*npd), GFP_KERNEL);
+	npd = kmemdup(pd, sizeof(struct s3c_ts_mach_info), GFP_KERNEL);
+	if (npd) {
+		memcpy(npd, pd, sizeof(*npd));
+		s3c_device_ts.dev.platform_data = npd;
+	} else {
+		printk(KERN_ERR "no memory for Touchscreen platform data\n");
+	}
+}
+
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/dev-usb.c android_2.6.29/arch/arm/plat-s3c/dev-usb.c
--- android_2.6.29_org/arch/arm/plat-s3c/dev-usb.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/dev-usb.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,50 @@
+/* linux/arch/arm/plat-s3c/dev-usb.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for USB host
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+
+static struct resource s3c_usb_resource[] = {
+	[0] = {
+		.start = S3C_PA_USBHOST,
+		.end   = S3C_PA_USBHOST + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_USBH,
+		.end   = IRQ_USBH,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+static u64 s3c_device_usb_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_usb = {
+	.name		  = "s3c2410-ohci",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_usb_resource),
+	.resource	  = s3c_usb_resource,
+	.dev              = {
+		.dma_mask = &s3c_device_usb_dmamask,
+		.coherent_dma_mask = 0xffffffffUL
+	}
+};
+
+EXPORT_SYMBOL(s3c_device_usb);
diff -urN android_2.6.29_org/arch/arm/plat-s3c/dma.c android_2.6.29/arch/arm/plat-s3c/dma.c
--- android_2.6.29_org/arch/arm/plat-s3c/dma.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/dma.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,86 @@
+/* linux/arch/arm/plat-s3c/dma.c
+ *
+ * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct s3c2410_dma_buf;
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+#include <plat/dma-plat.h>
+
+/* dma channel state information */
+struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
+struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
+
+/* s3c_dma_lookup_channel
+ *
+ * change the dma channel number given into a real dma channel id
+*/
+
+struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
+{
+	if (channel & DMACH_LOW_LEVEL)
+		return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
+	else
+		return s3c_dma_chan_map[channel];
+}
+
+/* do we need to protect the settings of the fields from
+ * irq?
+*/
+
+int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+	if (chan == NULL)
+		return -EINVAL;
+
+	pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
+
+	chan->op_fn = rtn;
+
+	return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_opfn);
+
+int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+	if (chan == NULL)
+		return -EINVAL;
+
+	pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
+
+	chan->callback_fn = rtn;
+
+	return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
+
+int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+	if (chan == NULL)
+		return -EINVAL;
+
+	chan->flags = flags;
+	return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_setflags);
diff -urN android_2.6.29_org/arch/arm/plat-s3c/gpio-config.c android_2.6.29/arch/arm/plat-s3c/gpio-config.c
--- android_2.6.29_org/arch/arm/plat-s3c/gpio-config.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/gpio-config.c	2009-04-10 12:46:50.000000000 +0900
@@ -13,6 +13,7 @@
 */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
 
@@ -38,6 +39,7 @@
 
 	return ret;
 }
+EXPORT_SYMBOL(s3c_gpio_cfgpin);
 
 int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
 {
@@ -56,6 +58,51 @@
 
 	return ret;
 }
+EXPORT_SYMBOL(s3c_gpio_setpull);
+
+int s3c_gpio_getpin(unsigned int pin)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        int offset, ret;
+
+        if (!chip)
+                return -EINVAL;
+
+        offset = pin - chip->chip.base;
+
+        local_irq_save(flags);
+        ret = __raw_readl(chip->base + 0x04);
+
+        ret >>= offset;
+        ret &= 1;
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c_gpio_getpin);
+
+void s3c_gpio_setpin(unsigned int pin, unsigned int to)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        int offset, ret;
+
+        if (!chip)
+                return -EINVAL;
+
+        offset = pin - chip->chip.base;
+
+        local_irq_save(flags);
+	ret = __raw_readl(chip->base +0x04);
+	ret &= ~(1 << offset);
+	ret |= to << offset;
+        __raw_writel(ret, chip->base + 0x04);
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(s3c_gpio_setpin);
 
 #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
 int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
diff -urN android_2.6.29_org/arch/arm/plat-s3c/gpio.c android_2.6.29/arch/arm/plat-s3c/gpio.c
--- android_2.6.29_org/arch/arm/plat-s3c/gpio.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/gpio.c	2009-04-10 11:13:25.000000000 +0900
@@ -16,7 +16,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <plat/gpio-core.h>
+#include <mach/gpio-core.h>
 
 #ifdef CONFIG_S3C_GPIO_TRACK
 struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
@@ -140,6 +140,15 @@
 	if (!gc->get)
 		gc->get = s3c_gpiolib_get;
 
+#ifdef CONFIG_PM
+	if (chip->pm != NULL) {
+		if (!chip->pm->save || !chip->pm->resume)
+			printk(KERN_ERR "gpio: %s has missing PM functions\n",
+			       gc->label);
+	} else
+		printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
+#endif
+
 	/* gpiochip_add() prints own failure message on error. */
 	ret = gpiochip_add(gc);
 	if (ret >= 0)
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/mach/cpu.h android_2.6.29/arch/arm/plat-s3c/include/mach/cpu.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/mach/cpu.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/mach/cpu.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,165 @@
+/*
+ * arch/arm/plat-s3c/include/mach/cpu.h
+ *
+ *  S3C cpu type detection
+ *
+ *  Copyright (C) 2008 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from OMAP cpu.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_S3C_CPU_H
+#define __ASM_ARCH_S3C_CPU_H
+
+extern unsigned int system_rev;
+
+#define S3C_SYSTEM_REV_ATAG (system_rev & 0xffff)
+#define S3C_SYSTEM_REV_CPU (system_rev & 0xffff0000)
+
+/*
+ * cpu_is_s3c24xx():	True for s3c2400, s3c2410, s3c2440 and so on
+ * cpu_is_s3c241x():	True fro s3c2410, s3c2412
+ * cpu_is_s3c244x():	True fro s3c2440, s3c2442, s3c2443
+ * cpu_is_s3c64xx():	True for s3c6400, s3c6410
+ */
+#define GET_S3C_CLASS	((system_rev >> 24) & 0xff)
+
+#define IS_S3C_CLASS(class, id)						\
+static inline int is_s3c ##class (void)					\
+{									\
+	return (GET_S3C_CLASS == (id)) ? 1 : 0;				\
+}
+
+#define GET_S3C_SUBCLASS	((system_rev >> 20) & 0xfff)
+
+#define IS_S3C_SUBCLASS(subclass, id)					\
+static inline int is_s3c ##subclass (void)				\
+{									\
+	return (GET_S3C_SUBCLASS == (id)) ? 1 : 0;			\
+}
+
+IS_S3C_CLASS(24xx, 0x24)
+IS_S3C_CLASS(64xx, 0x64)
+
+IS_S3C_SUBCLASS(241x, 0x241)
+IS_S3C_SUBCLASS(244x, 0x244)
+
+#define cpu_is_s3c24xx()		0
+#define cpu_is_s3c241x()		0
+#define cpu_is_s3c244x()		0
+#define cpu_is_s3c64xx()		0
+
+#if defined(CONFIG_ARCH_S3C2410)
+# undef  cpu_is_s3c24xx
+# undef  cpu_is_s3c241x
+# undef  cpu_is_s3c244x
+# define cpu_is_s3c24xx()		is_s3c24xx()
+# define cpu_is_s3c241x()		is_s3c241x()
+# define cpu_is_s3c244x()		is_s3c244x()
+#endif
+
+#if defined(CONFIG_ARCH_S3C64XX)
+# undef  cpu_is_s3c64xx
+# define cpu_is_s3c64xx()		is_s3c64xx()
+#endif
+
+/*
+ * Macros to detect individual cpu types.
+ * cpu_is_s3c2410():	True for s3c2410
+ * cpu_is_s3c2440():	True for s3c2440
+ * cpu_is_s3c6400():	True for s3c6400
+ * cpu_is_s3c6410():	True for s3c6410
+ *
+ * Exception:
+ * Store Revision A to 1
+ * s3c2410a -> s3c2411
+ * s3c2440a -> s3c2441
+ */
+
+#define GET_S3C_TYPE	((system_rev >> 16) & 0xffff)
+
+#define IS_S3C_TYPE(type, id)						\
+static inline int is_s3c ##type (void)					\
+{									\
+	return (GET_S3C_TYPE == (id)) ? 1 : 0;				\
+}
+
+IS_S3C_TYPE(2400, 0x2400)
+IS_S3C_TYPE(2410, 0x2410)
+IS_S3C_TYPE(2410a, 0x2411)
+IS_S3C_TYPE(2412, 0x2412)
+IS_S3C_TYPE(2440, 0x2440)
+IS_S3C_TYPE(2440a, 0x2441)
+IS_S3C_TYPE(2442, 0x2442)
+IS_S3C_TYPE(2443, 0x2443)
+IS_S3C_TYPE(6400, 0x6400)
+IS_S3C_TYPE(6410, 0x6410)
+
+#define cpu_is_s3c2400()		0
+#define cpu_is_s3c2410()		0
+#define cpu_is_s3c2410a()		0
+#define cpu_is_s3c2412()		0
+#define cpu_is_s3c2440()		0
+#define cpu_is_s3c2440a()		0
+#define cpu_is_s3c2442()		0
+#define cpu_is_s3c2443()		0
+#define cpu_is_s3c6400()		0
+#define cpu_is_s3c6410()		0
+
+#if defined(CONFIG_ARCH_S3C2410)
+# undef  cpu_is_s3c2400
+# define cpu_is_s3c2400()		is_s3c2400()
+#endif
+
+#if defined(CONFIG_CPU_S3C2410)
+# undef  cpu_is_s3c2410
+# undef  cpu_is_s3c2410a
+# define cpu_is_s3c2410()		is_s3c2410()
+# define cpu_is_s3c2410a()		is_s3c2410a()
+#endif
+
+#if defined(CONFIG_CPU_S3C2412)
+# undef  cpu_is_s3c2412
+# define cpu_is_s3c2412()		is_s3c2412()
+#endif
+
+#if defined(CONFIG_CPU_S3C2440)
+# undef  cpu_is_s3c2440
+# undef  cpu_is_s3c2440a
+# define cpu_is_s3c2440()		is_s3c2440()
+# define cpu_is_s3c2440a()		is_s3c2440a()
+#endif
+
+#if defined(CONFIG_CPU_S3C2442)
+# undef  cpu_is_s3c2442
+# define cpu_is_s3c2442()		is_s3c2442()
+#endif
+
+#if defined(CONFIG_CPU_S3C2443)
+# undef  cpu_is_s3c2443
+# define cpu_is_s3c2443()		is_s3c2443()
+#endif
+
+#if defined(CONFIG_ARCH_S3C64XX)
+# undef  cpu_is_s3c6400
+# undef  cpu_is_s3c6410
+# define cpu_is_s3c6400()		is_s3c6400()
+# define cpu_is_s3c6410()		is_s3c6410()
+#endif
+
+#endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/adc.h android_2.6.29/arch/arm/plat-s3c/include/plat/adc.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/adc.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/adc.h	2009-04-10 11:13:25.000000000 +0900
@@ -16,6 +16,17 @@
 
 struct s3c_adc_client;
 
+struct s3c_adc_mach_info
+{
+	/* if you need to use some platform data, add in here*/
+	int delay;
+	int presc;
+	int resolution;
+};
+
+void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd);
+
+
 extern int s3c_adc_start(struct s3c_adc_client *client,
 			 unsigned int channel, unsigned int nr_samples);
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/audio.h android_2.6.29/arch/arm/plat-s3c/include/plat/audio.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/audio.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/audio.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,45 @@
+/* arch/arm/mach-s3c2410/include/mach/audio.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ *	http://www.simtec.co.uk/products/SWLINUX/
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Audio platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_AUDIO_H
+#define __ASM_ARCH_AUDIO_H __FILE__
+
+/* struct s3c24xx_iis_ops
+ *
+ * called from the s3c24xx audio core to deal with the architecture
+ * or the codec's setup and control.
+ *
+ * the pointer to itself is passed through in case the caller wants to
+ * embed this in an larger structure for easy reference to it's context.
+*/
+
+struct s3c24xx_iis_ops {
+	struct module *owner;
+
+	int	(*startup)(struct s3c24xx_iis_ops *me);
+	void	(*shutdown)(struct s3c24xx_iis_ops *me);
+	int	(*suspend)(struct s3c24xx_iis_ops *me);
+	int	(*resume)(struct s3c24xx_iis_ops *me);
+
+	int	(*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
+	int	(*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
+	int	(*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt);
+};
+
+struct s3c24xx_platdata_iis {
+	const char		*codec_clk;
+	struct s3c24xx_iis_ops	*ops;
+	int			(*match_dev)(struct device *dev);
+};
+
+#endif /* __ASM_ARCH_AUDIO_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/clock.h android_2.6.29/arch/arm/plat-s3c/include/plat/clock.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/clock.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/clock.h	2009-04-10 11:13:25.000000000 +0900
@@ -50,6 +50,7 @@
 extern struct clk clk_ext;
 
 /* S3C64XX specific clocks */
+extern struct clk clk_h2;
 extern struct clk clk_27m;
 extern struct clk clk_48m;
 
@@ -80,6 +81,7 @@
 
 /* S3C64XX specific functions and clocks */
 
+extern int s3c64xx_hclk_ctrl(struct clk *clk, int enable);
 extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
 
 /* Init for pwm clock code */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/cpu.h android_2.6.29/arch/arm/plat-s3c/include/plat/cpu.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/cpu.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/cpu.h	2009-04-10 11:13:25.000000000 +0900
@@ -12,7 +12,11 @@
 
 /* todo - fix when rmk changes iodescs to use `void __iomem *` */
 
+#if defined (CONFIG_ARCH_S3C2410)
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
+#elif defined(CONFIG_ARCH_S3C64XX)
+#define IODESC_ENT(x) { (unsigned long)S3C64XX_VA_##x, __phys_to_pfn(S3C64XX_PA_##x), S3C64XX_SZ_##x, MT_DEVICE }
+#endif
 
 #ifndef MHZ
 #define MHZ (1000*1000)
@@ -69,3 +73,6 @@
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;
+extern struct sysdev_class s3c6410_sysclass;
+extern struct sysdev_class s3c64xx_sysclass;
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/devs.h android_2.6.29/arch/arm/plat-s3c/include/plat/devs.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/devs.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/devs.h	2009-04-10 12:28:19.000000000 +0900
@@ -16,6 +16,10 @@
 	unsigned long		 nr_resources;
 };
 
+struct s3c_plat_otg_data {
+	int		phyclk;
+};
+
 extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
 
@@ -24,6 +28,7 @@
 
 extern struct platform_device s3c_device_timer[];
 
+extern struct platform_device s3c_device_nand;
 extern struct platform_device s3c_device_fb;
 extern struct platform_device s3c_device_usb;
 extern struct platform_device s3c_device_lcd;
@@ -45,10 +50,11 @@
 
 extern struct platform_device s3c_device_usbgadget;
 
+extern struct platform_device s3c_device_ts;
+
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
 
 extern struct platform_device s3c_device_camif;
-
 #endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/dma-core.h android_2.6.29/arch/arm/plat-s3c/include/plat/dma-core.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/dma-core.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/dma-core.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,22 @@
+/* arch/arm/plat-s3c/include/plat/dma.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * Samsung S3C DMA core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
+
+extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
+
+/* the currently allocated channel information */
+extern struct s3c2410_dma_chan s3c2410_chans[];
+
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/dma.h android_2.6.29/arch/arm/plat-s3c/include/plat/dma.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/dma.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/dma.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,128 @@
+/* arch/arm/plat-s3c/include/plat/dma.h
+ *
+ * Copyright (C) 2003,2004,2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+enum s3c2410_dma_buffresult {
+	S3C2410_RES_OK,
+	S3C2410_RES_ERR,
+	S3C2410_RES_ABORT
+};
+
+enum s3c2410_dmasrc {
+	S3C2410_DMASRC_HW,		/* source is memory */
+	S3C2410_DMASRC_MEM		/* source is hardware */
+};
+
+/* enum s3c2410_chan_op
+ *
+ * operation codes passed to the DMA code by the user, and also used
+ * to inform the current channel owner of any changes to the system state
+*/
+
+enum s3c2410_chan_op {
+	S3C2410_DMAOP_START,
+	S3C2410_DMAOP_STOP,
+	S3C2410_DMAOP_PAUSE,
+	S3C2410_DMAOP_RESUME,
+	S3C2410_DMAOP_FLUSH,
+	S3C2410_DMAOP_TIMEOUT,		/* internal signal to handler */
+	S3C2410_DMAOP_STARTED,		/* indicate channel started */
+};
+
+struct s3c2410_dma_client {
+	char                *name;
+};
+
+struct s3c2410_dma_chan;
+
+/* s3c2410_dma_cbfn_t
+ *
+ * buffer callback routine type
+*/
+
+typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
+				   void *buf, int size,
+				   enum s3c2410_dma_buffresult result);
+
+typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
+				   enum s3c2410_chan_op );
+
+
+
+/* s3c2410_dma_request
+ *
+ * request a dma channel exclusivley
+*/
+
+extern int s3c2410_dma_request(unsigned int channel,
+			       struct s3c2410_dma_client *, void *dev);
+
+
+/* s3c2410_dma_ctrl
+ *
+ * change the state of the dma channel
+*/
+
+extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
+
+/* s3c2410_dma_setflags
+ *
+ * set the channel's flags to a given state
+*/
+
+extern int s3c2410_dma_setflags(unsigned int channel,
+				unsigned int flags);
+
+/* s3c2410_dma_free
+ *
+ * free the dma channel (will also abort any outstanding operations)
+*/
+
+extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
+
+/* s3c2410_dma_enqueue
+ *
+ * place the given buffer onto the queue of operations for the channel.
+ * The buffer must be allocated from dma coherent memory, or the Dcache/WB
+ * drained before the buffer is given to the DMA system.
+*/
+
+extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
+			       dma_addr_t data, int size);
+
+
+/* s3c2410_dma_config
+ *
+ * configure the dma channel
+*/
+
+extern int s3c2410_dma_config(unsigned int channel, int xferunit);
+
+/* s3c2410_dma_devconfig
+ *
+ * configure the device we're talking to
+*/
+
+extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
+				 unsigned long devaddr);
+
+/* s3c2410_dma_getposition
+ *
+ * get the position that the dma transfer is currently at
+*/
+
+extern int s3c2410_dma_getposition(unsigned int channel,
+				   dma_addr_t *src, dma_addr_t *dest);
+
+extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
+extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
+
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/gpio-cfg.h android_2.6.29/arch/arm/plat-s3c/include/plat/gpio-cfg.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/gpio-cfg.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/gpio-cfg.h	2009-04-10 12:46:25.000000000 +0900
@@ -107,4 +107,6 @@
 */
 extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
 
+extern int s3c_gpio_getpin(unsigned int pin);
+extern void s3c_gpio_setpin(unsigned int pin, unsigned int to);
 #endif /* __PLAT_GPIO_CFG_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/gpio-core.h android_2.6.29/arch/arm/plat-s3c/include/plat/gpio-core.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/gpio-core.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/gpio-core.h	2009-04-10 11:13:25.000000000 +0900
@@ -20,6 +20,19 @@
  * specific code.
 */
 
+struct s3c_gpio_chip;
+
+/**
+ * struct s3c_gpio_pm - power management (suspend/resume) information
+ * @save: Routine to save the state of the GPIO block
+ * @resume: Routine to resume the GPIO block.
+ */
+struct s3c_gpio_pm {
+	void (*save)(struct s3c_gpio_chip *chip);
+	void (*resume)(struct s3c_gpio_chip *chip);
+};
+
+
 struct s3c_gpio_cfg;
 
 /**
@@ -27,6 +40,7 @@
  * @chip: The chip structure to be exported via gpiolib.
  * @base: The base pointer to the gpio configuration registers.
  * @config: special function and pull-resistor control information.
+ * @pm_save: Save information for suspend/resume support.
  *
  * This wrapper provides the necessary information for the Samsung
  * specific gpios being registered with gpiolib.
@@ -34,7 +48,11 @@
 struct s3c_gpio_chip {
 	struct gpio_chip	chip;
 	struct s3c_gpio_cfg	*config;
+	struct s3c_gpio_pm	*pm;
 	void __iomem		*base;
+#ifdef CONFIG_PM
+	u32			pm_save[4];
+#endif
 };
 
 static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
@@ -75,3 +93,16 @@
 
 static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
 #endif
+
+#ifdef CONFIG_PM
+extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
+#define __gpio_pm(x) x
+#else
+#define s3c_gpio_pm_1bit NULL
+#define s3c_gpio_pm_2bit NULL
+#define s3c_gpio_pm_4bit NULL
+#define __gpio_pm(x) NULL
+
+#endif /* CONFIG_PM */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/map-base.h android_2.6.29/arch/arm/plat-s3c/include/plat/map-base.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/map-base.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/map-base.h	2009-04-16 20:11:41.000000000 +0900
@@ -35,6 +35,14 @@
 #define S3C_VA_MEM	S3C_ADDR(0x00200000)	/* system control */
 #define S3C_VA_TIMER	S3C_ADDR(0x00300000)	/* timer block */
 #define S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	/* watchdog */
+#define S3C_VA_GPIO	S3C_ADDR(0x00500000)
+#define S3C_VA_MODEM S3C_ADDR(0x00600000)
+#define S3C_VA_HOSTIFA	S3C_ADDR(0x00b00000)
+#define S3C_VA_HOSTIFB	S3C_ADDR(0x00C00000)
 #define S3C_VA_UART	S3C_ADDR(0x01000000)	/* UART */
+#define S3C_VA_OTG	S3C_ADDR(0x03900000)	/* OTG */
+#define S3C_VA_OTGSFR	S3C_ADDR(0x03a00000)	/* OTGSFR */
+#define S3C_VA_CS89X0	S3C_ADDR(0x03b00000)	/* CS89XX */
+#define S3C_VA_SMSC9220	S3C_ADDR(0x03b00000)	/* SMSC9220 */
 
 #endif /* __ASM_PLAT_MAP_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/nand.h android_2.6.29/arch/arm/plat-s3c/include/plat/nand.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/nand.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/nand.h	2009-04-10 11:26:42.000000000 +0900
@@ -21,11 +21,14 @@
  * partitions	 = mtd partition list
 */
 
+#define S3C2410_NAND_BBT	0x0001
+
 struct s3c2410_nand_set {
 	unsigned int		disable_ecc : 1;
 
 	int			nr_chips;
 	int			nr_partitions;
+	unsigned int		flags;
 	char			*name;
 	int			*nr_map;
 	struct mtd_partition	*partitions;
@@ -44,7 +47,15 @@
 	int			nr_sets;
 	struct s3c2410_nand_set *sets;
 
+	/* force software_ecc at runtime */
+	int	software_ecc;
+
 	void			(*select_chip)(struct s3c2410_nand_set *,
 					       int chip);
 };
 
+struct s3c_nand_mtd_info {
+	uint chip_nr;
+	uint mtd_part_nr;
+	struct mtd_partition *partition;
+};
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/partition.h android_2.6.29/arch/arm/plat-s3c/include/plat/partition.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/partition.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/partition.h	2009-04-10 12:11:04.000000000 +0900
@@ -0,0 +1,41 @@
+/* arch/arm/plat-s3c/include/plat/partition.h
+ *
+ * Copyright (c) 2008 Samsung Electronics
+ *
+ * Partition information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct mtd_partition s3c_partition_info[] = {
+        {
+                .name		= "Bootloader",
+                .offset		= 0,
+                .size		= (256*SZ_1K),
+                .mask_flags	= MTD_CAP_NANDFLASH,
+        },
+        {
+                .name		= "Kernel",
+                .offset		= (256*SZ_1K),
+                .size		= (4*SZ_1M) - (256*SZ_1K),
+                .mask_flags	= MTD_CAP_NANDFLASH,
+        },
+        {
+                .name		= "Rootfs",
+                .offset		= (4*SZ_1M),
+                .size		= (64*SZ_1M),
+        },
+        {
+                .name		= "File System",
+                .offset		= MTDPART_OFS_APPEND,
+                .size		= MTDPART_SIZ_FULL,
+        }
+};
+
+struct s3c_nand_mtd_info s3c_nand_mtd_part_info = {
+	.chip_nr = 1,
+	.mtd_part_nr = ARRAY_SIZE(s3c_partition_info),
+	.partition = s3c_partition_info,
+};
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/pm.h android_2.6.29/arch/arm/plat-s3c/include/plat/pm.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/pm.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/pm.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,184 @@
+/* linux/include/asm-arm/plat-s3c24xx/pm.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *	http://armlinux.simtec.co.uk/
+ *	Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sysdev.h>
+
+/* s3c_pm_init
+ *
+ * called from board at initialisation time to setup the power
+ * management
+*/
+
+#ifdef CONFIG_PM
+
+extern __init int s3c_pm_init(void);
+
+#else
+
+static inline int s3c_pm_init(void)
+{
+	return 0;
+}
+#endif
+
+/* configuration for the IRQ mask over sleep */
+extern unsigned long s3c_irqwake_intmask;
+extern unsigned long s3c_irqwake_eintmask;
+
+/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
+extern unsigned long s3c_irqwake_intallow;
+extern unsigned long s3c_irqwake_eintallow;
+
+/* per-cpu sleep functions */
+
+extern void (*pm_cpu_prep)(void);
+extern void (*pm_cpu_sleep)(void);
+
+/* Flags for PM Control */
+
+extern unsigned long s3c_pm_flags;
+
+extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
+
+/* from sleep.S */
+
+extern int  s3c_cpu_save(unsigned long *saveblk);
+extern void s3c_cpu_resume(void);
+
+extern void s3c2410_cpu_suspend(void);
+
+extern unsigned long s3c_sleep_save_phys;
+
+/* sleep save info */
+
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+	void __iomem	*reg;
+	unsigned long	val;
+};
+
+#define SAVE_ITEM(x) \
+	{ .reg = (x) }
+
+/**
+ * struct pm_uart_save - save block for core UART
+ * @ulcon: Save value for S3C2410_ULCON
+ * @ucon: Save value for S3C2410_UCON
+ * @ufcon: Save value for S3C2410_UFCON
+ * @umcon: Save value for S3C2410_UMCON
+ * @ubrdiv: Save value for S3C2410_UBRDIV
+ *
+ * Save block for UART registers to be held over sleep and restored if they
+ * are needed (say by debug).
+*/
+struct pm_uart_save {
+	u32	ulcon;
+	u32	ucon;
+	u32	ufcon;
+	u32	umcon;
+	u32	ubrdiv;
+	u32	udivslot;
+};
+
+/* helper functions to save/restore lists of registers. */
+
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
+
+#ifdef CONFIG_PM
+extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
+extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
+extern int s3c24xx_irq_resume(struct sys_device *dev);
+#else
+#define s3c_irqext_wake NULL
+#define s3c24xx_irq_suspend NULL
+#define s3c24xx_irq_resume  NULL
+#endif
+
+/* PM debug functions */
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+/**
+ * s3c_pm_dbg() - low level debug function for use in suspend/resume.
+ * @msg: The message to print.
+ *
+ * This function is used mainly to debug the resume process before the system
+ * can rely on printk/console output. It uses the low-level debugging output
+ * routine printascii() to do its work.
+ */
+extern void s3c_pm_dbg(const char *msg, ...);
+
+#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
+#else
+#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
+#endif
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+/**
+ * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
+ * @set: set bits for the state of the LEDs
+ * @clear: clear bits for the state of the LEDs.
+ */
+extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
+
+#else
+static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
+#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
+
+/* suspend memory checking */
+
+#ifdef CONFIG_S3C2410_PM_CHECK
+extern void s3c_pm_check_prepare(void);
+extern void s3c_pm_check_restore(void);
+extern void s3c_pm_check_cleanup(void);
+extern void s3c_pm_check_store(void);
+#else
+#define s3c_pm_check_prepare() do { } while(0)
+#define s3c_pm_check_restore() do { } while(0)
+#define s3c_pm_check_cleanup() do { } while(0)
+#define s3c_pm_check_store()   do { } while(0)
+#endif
+
+/**
+ * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
+ *
+ * Setup all the necessary GPIO pins for waking the system on external
+ * interrupt.
+ */
+extern void s3c_pm_configure_extint(void);
+
+/**
+ * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
+ *
+ * Restore the state of the GPIO pins after sleep, which may involve ensuring
+ * that we do not glitch the state of the pins from that the bootloader's
+ * resume code has done.
+*/
+extern void s3c_pm_restore_gpios(void);
+
+/**
+ * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
+ *
+ * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
+ */
+extern void s3c_pm_save_gpios(void);
+
+extern void s3c_pm_save_core(void);
+extern void s3c_pm_restore_core(void);
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/pwm.h android_2.6.29/arch/arm/plat-s3c/include/plat/pwm.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/pwm.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/pwm.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,45 @@
+#ifndef __S3C2410_PWM_H
+#define __S3C2410_PWM_H
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <mach/io.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <plat/regs-timer.h>
+
+enum pwm_timer {
+	PWM0,
+	PWM1,
+	PWM2,
+	PWM3,
+	PWM4
+};
+
+struct s3c2410_pwm {
+	enum pwm_timer timerid;
+	struct clk *pclk;
+	unsigned long pclk_rate;
+	unsigned long prescaler;
+	unsigned long divider;
+	unsigned long counter;
+	unsigned long comparer;
+};
+
+struct s3c24xx_pwm_platform_data{
+        /* callback to attach platform children (to enforce suspend / resume
+         * ordering */
+        void (*attach_child_devices)(struct device *parent_device);
+};
+
+int s3c2410_pwm_init(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_enable(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_disable(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_start(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_stop(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_dumpregs(void);
+
+#endif /* __S3C2410_PWM_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-adc.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-adc.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-adc.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-adc.h	2009-04-10 11:13:25.000000000 +0900
@@ -55,6 +55,65 @@
 #define S3C2410_ADCDAT1_XY_PST		(0x3<<12)
 #define S3C2410_ADCDAT1_YPDATA_MASK	(0x03FF)
 
+/*--------------------------- Common definitions for S3C  ---------------------------*/
+/* The following definitions will be applied to S3C24XX, S3C64XX, S5PC1XX.	     */
+/*-----------------------------------------------------------------------------------*/
+
+#define S3C_ADCREG(x) 			(x)
+
+#define S3C_ADCCON	   		S3C_ADCREG(0x00)
+#define S3C_ADCTSC	  		S3C_ADCREG(0x04)
+#define S3C_ADCDLY	   		S3C_ADCREG(0x08)
+#define S3C_ADCDAT0	   		S3C_ADCREG(0x0C)
+#define S3C_ADCDAT1	   		S3C_ADCREG(0x10)
+#define S3C_ADCUPDN			S3C_ADCREG(0x14)
+#define S3C_ADCMUX			S3C_ADCREG(0x18)
+#define S3C_ADCCLRINT			S3C_ADCREG(0x18)
+#define S3C_ADCCLRWK			S3C_ADCREG(0x20)
+
+
+/* ADCCON Register Bits */
+#define S3C_ADCCON_RESSEL_10BIT		(0x0<<16)
+#define S3C_ADCCON_RESSEL_12BIT		(0x1<<16)
+#define S3C_ADCCON_ECFLG		(1<<15)
+#define S3C_ADCCON_PRSCEN		(1<<14)
+#define S3C_ADCCON_PRSCVL(x)		(((x)&0xFF)<<6)
+#define S3C_ADCCON_PRSCVLMASK		(0xFF<<6)
+#define S3C_ADCCON_SELMUX(x)		(((x)&0x7)<<3)
+#define S3C_ADCCON_SELMUX_1(x)		(((x)&0xF)<<0)
+#define S3C_ADCCON_MUXMASK		(0x7<<3)
+#define S3C_ADCCON_RESSEL_10BIT_1	(0x0<<3)
+#define S3C_ADCCON_RESSEL_12BIT_1	(0x1<<3)
+#define S3C_ADCCON_STDBM		(1<<2)
+#define S3C_ADCCON_READ_START		(1<<1)
+#define S3C_ADCCON_ENABLE_START		(1<<0)
+#define S3C_ADCCON_STARTMASK		(0x3<<0)
+
+
+/* ADCTSC Register Bits */
+#define S3C_ADCTSC_UD_SEN		(1<<8)
+#define S3C_ADCTSC_YM_SEN		(1<<7)
+#define S3C_ADCTSC_YP_SEN		(1<<6)
+#define S3C_ADCTSC_XM_SEN		(1<<5)
+#define S3C_ADCTSC_XP_SEN		(1<<4)
+#define S3C_ADCTSC_PULL_UP_DISABLE	(1<<3)
+#define S3C_ADCTSC_AUTO_PST		(1<<2)
+#define S3C_ADCTSC_XY_PST(x)		(((x)&0x3)<<0)
+
+/* ADCDAT0 Bits */
+#define S3C_ADCDAT0_UPDOWN		(1<<15)
+#define S3C_ADCDAT0_AUTO_PST		(1<<14)
+#define S3C_ADCDAT0_XY_PST		(0x3<<12)
+#define S3C_ADCDAT0_XPDATA_MASK		(0x03FF)
+#define S3C_ADCDAT0_XPDATA_MASK_12BIT	(0x0FFF)
+
+/* ADCDAT1 Bits */
+#define S3C_ADCDAT1_UPDOWN		(1<<15)
+#define S3C_ADCDAT1_AUTO_PST		(1<<14)
+#define S3C_ADCDAT1_XY_PST		(0x3<<12)
+#define S3C_ADCDAT1_YPDATA_MASK		(0x03FF)
+#define S3C_ADCDAT1_YPDATA_MASK_12BIT	(0x0FFF)
+
 #endif /* __ASM_ARCH_REGS_ADC_H */
 
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-iis.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-iis.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-iis.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-iis.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,126 @@
+/* linux/include/asm-arm/arch-s3c64XX/regs-iis.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C64XX IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_IIS_H
+#define __ASM_ARCH_REGS_IIS_H
+
+#define S3C64XX_IIS0REG(x)	((x) + S3C64XX_PA_IIS_V40)
+
+//#define S3C_IIS0CON		S3C64XX_IIS0REG(0x00)
+//#define S3C_IIS0MOD		S3C64XX_IIS0REG(0x04)
+//#define S3C_IIS0FIC		S3C64XX_IIS0REG(0x08)
+//#define S3C_IIS0PSR		S3C64XX_IIS0REG(0x0C)
+//#define S3C_IIS0TXD		S3C64XX_IIS0REG(0x10)
+//#define S3C_IIS0RXD		S3C64XX_IIS0REG(0x14)
+
+#define S3C64XX_IIS0CON		(0x00)
+#define S3C64XX_IIS0MOD		(0x04)
+#define S3C64XX_IIS0FIC		(0x08)
+#define S3C64XX_IIS0PSR		(0x0C)
+#define S3C64XX_IIS0TXD		(0x10)
+#define S3C64XX_IIS0RXD		(0x14)
+
+#define S3C64XX_IISCON_LRINDEX		(1<<8)
+#define S3C64XX_IISCON_TXFIFORDY	(1<<7)
+#define S3C64XX_IISCON_RXFIFORDY	(1<<6)
+#define S3C64XX_IISCON_TXDMAEN		(1<<5)
+#define S3C64XX_IISCON_RXDMAEN		(1<<4)
+#define S3C64XX_IISCON_TXIDLE		(1<<3)
+#define S3C64XX_IISCON_RXIDLE		(1<<2)
+#define S3C64XX_IISCON_PSCEN		(1<<1)
+#define S3C64XX_IISCON_IISEN		(1<<0)
+
+//#define S3C64XX_IISMOD_MPLL	  (1<<9)
+#define S3C64XX_IISMOD_MPLL		(0x01<<10)
+#define S3C64XX_IISMOD_SLAVE		(1<<8)
+#define S3C64XX_IISMOD_NOXFER		(0<<6)
+#define S3C64XX_IISMOD_RXMODE		(1<<6)
+#define S3C64XX_IISMOD_TXMODE		(2<<6)
+#define S3C64XX_IISMOD_TXRXMODE		(3<<6)
+#define S3C64XX_IISMOD_LR_LLOW		(0<<5)
+#define S3C64XX_IISMOD_LR_RLOW		(1<<5)
+#define S3C64XX_IISMOD_IIS		(0<<4)
+#define S3C64XX_IISMOD_MSB		(1<<4)
+#define S3C64XX_IISMOD_8BIT		(0<<3)
+#define S3C64XX_IISMOD_16BIT		(1<<3)
+#define S3C64XX_IISMOD_BITMASK		(1<<3)
+#define S3C64XX_IISMOD_256FS		(0<<2)
+#define S3C64XX_IISMOD_384FS		(1<<2)
+#define S3C64XX_IISMOD_16FS		(0<<0)
+#define S3C64XX_IISMOD_32FS		(1<<0)
+#define S3C64XX_IISMOD_48FS		(2<<0)
+#define S3C64XX_IISMOD_FS_MASK		(3<<0)
+
+#define S3C64XX_IIS0MOD_DCE_MASK	(0x3<<16)
+#define S3C64XX_IIS0MOD_DCE_SD2		(0x1<<17)
+#define S3C64XX_IIS0MOD_DCE_SD1		(0x1<<16)
+#define S3C64XX_IIS0MOD_BLC_MASK	(0x3<<13)
+#define S3C64XX_IIS0MOD_BLC_16BIT	(0x0<<13)
+#define S3C64XX_IIS0MOD_BLC_08BIT	(0x1<<13)
+#define S3C64XX_IIS0MOD_BLC_24BIT	(0x2<<13)
+#define S3C64XX_IIS0MOD_CLK_MASK	(0x7<<10)
+#define S3C64XX_IIS0MOD_INTERNAL_CLK	(0x0<<12)
+#define S3C64XX_IIS0MOD_EXTERNAL_CLK	(0x1<<12)
+#define S3C64XX_IIS0MOD_IMS_INTERNAL_MASTER	(0x0<<10)
+#define S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER	(0x1<<10)
+#define S3C64XX_IIS0MOD_IMS_SLAVE	(0x2<<10)
+#define S3C64XX_IIS0MOD_MODE_MASK	(0x3<<8)
+#define S3C64XX_IIS0MOD_TXMODE		(0x0<<8)
+#define S3C64XX_IIS0MOD_RXMODE		(0x1<<8)
+#define S3C64XX_IIS0MOD_TXRXMODE	(0x2<<8)
+#define S3C64XX_IIS0MOD_FM_MASK		(0x3<<5)
+#define S3C64XX_IIS0MOD_IIS		(0x0<<5)
+#define S3C64XX_IIS0MOD_MSB		(0x1<<5)
+#define S3C64XX_IIS0MOD_LSB		(0x2<<5)
+#define S3C64XX_IIS0MOD_FS_MASK		(0x3<<3)
+#define S3C64XX_IIS0MOD_768FS		(0x3<<3)
+#define S3C64XX_IIS0MOD_384FS		(0x2<<3)
+#define S3C64XX_IIS0MOD_512FS		(0x1<<3)
+#define S3C64XX_IIS0MOD_256FS		(0x0<<3)
+#define S3C64XX_IIS0MOD_BFS_MASK	(0x3<<1)
+#define S3C64XX_IIS0MOD_48FS		(0x1<<1)
+#define S3C64XX_IIS0MOD_32FS		(0x0<<1)
+
+#define S3C64XX_IISPSR			(0x08)
+#define S3C64XX_IISPSR_INTMASK		(31<<5)
+#define S3C64XX_IISPSR_INTSHIFT		(5)
+#define S3C64XX_IISPSR_EXTMASK		(31<<0)
+#define S3C64XX_IISPSR_EXTSHFIT		(0)
+
+#define S3C64XX_IISFCON		(0x0c)
+
+#define S3C64XX_IISFCON_TXDMA		(1<<15)
+#define S3C64XX_IISFCON_RXDMA		(1<<14)
+#define S3C64XX_IISFCON_TXENABLE	(1<<13)
+#define S3C64XX_IISFCON_RXENABLE	(1<<12)
+#define S3C64XX_IISFCON_TXMASK		(0x3f << 6)
+#define S3C64XX_IISFCON_TXSHIFT		(6)
+#define S3C64XX_IISFCON_RXMASK		(0x3f)
+#define S3C64XX_IISFCON_RXSHIFT		(0)
+
+#define S3C64XX_IISFIFO		(0x10)
+#define S3C64XX_IISFIFORX	(0x14)
+
+#define S3C64XX_IIS0CON_I2SACTIVE	(0x1<<0)
+#define S3C64XX_IIS0CON_RXDMACTIVE	(0x1<<1)
+#define S3C64XX_IIS0CON_I2SACTIVE	(0x1<<0)
+#define S3C64XX_IIS0CON_TXDMACTIVE	(0x1<<2)
+
+#define S3C64XX_IIS_TX_FLUSH	(0x1<<15)
+#define S3C64XX_IIS_RX_FLUSH	(0x1<<7)
+
+#define S3C64XX_IISCON_FTXURINTEN 	(0x1<<16)
+
+#define S3C64XX_IIS0MOD_24BIT		(0x2<<13)
+#define S3C64XX_IIS0MOD_8BIT		(0x1<<13)
+#define S3C64XX_IIS0MOD_16BIT		(0x0<<13)
+#endif /* __ASM_ARCH_REGS_IIS_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-lcd.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-lcd.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-lcd.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-lcd.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,495 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-lcd.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef ___ASM_ARCH_REGS_LCD_H
+#define ___ASM_ARCH_REGS_LCD_H
+
+#include <plat/map-base.h>
+
+/***************************************************************************/
+/* LCD Registers for S3C2443/2450/S3C6400/6410 */
+#define S3C_LCDREG(x)		((x) + S3C_VA_LCD)
+
+/* LCD control registers */
+#define S3C_VIDCON0		S3C_LCDREG(0x00)  	/* Video control 0 register */
+#define S3C_VIDCON1		S3C_LCDREG(0x04)  	/* Video control 1 register */
+
+#if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C_VIDTCON0		S3C_LCDREG(0x08)  	/* LCD CONTROL 1 */
+#define S3C_VIDTCON1		S3C_LCDREG(0x0C)  	/* LCD CONTROL 1 */
+#define S3C_VIDTCON2		S3C_LCDREG(0x10) 	/* LCD CONTROL 1 */
+#define S3C_WINCON0		S3C_LCDREG(0x14)  	/* LCD CONTROL 1 */
+#define S3C_WINCON1		S3C_LCDREG(0x18)  	/* LCD CONTROL 1 */
+#define S3C_VIDOSD0A		S3C_LCDREG(0x28)  	/* LCD CONTROL 1 */
+#define S3C_VIDOSD0B		S3C_LCDREG(0x2C)  	/* LCD CONTROL 1 */
+#define S3C_VIDOSD0C		S3C_LCDREG(0x30)  	/* LCD CONTROL 1 */
+#define S3C_VIDOSD1A		S3C_LCDREG(0x34)  	/* LCD CONTROL 1 */
+#define S3C_VIDOSD1B		S3C_LCDREG(0x38)  	/* LCD CONTROL 1 */
+#define S3C_VIDOSD1C		S3C_LCDREG(0x3C)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD0B0	S3C_LCDREG(0x64)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD0B1	S3C_LCDREG(0x68)  	/* LCD CONTROL 1 */
+#define S3C_VIDW01ADD0		S3C_LCDREG(0x6C)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD1B0	S3C_LCDREG(0x7C)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD1B1	S3C_LCDREG(0x80)  	/* LCD CONTROL 1 */
+#define S3C_VIDW01ADD1		S3C_LCDREG(0x84)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD2B0	S3C_LCDREG(0x94)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD2B1	S3C_LCDREG(0x98)  	/* LCD CONTROL 1 */
+#define S3C_VIDW01ADD2		S3C_LCDREG(0x9C)  	/* LCD CONTROL 1 */
+#define S3C_VIDINTCON		S3C_LCDREG(0xAC)  	/* LCD CONTROL 1 */
+#define S3C_W1KEYCON0		S3C_LCDREG(0xB0)  	/* LCD CONTROL 1 */
+#define S3C_W1KEYCON1		S3C_LCDREG(0xB4)  	/* LCD CONTROL 1 */
+#define S3C_WIN0MAP		S3C_LCDREG(0xD0)  	/* LCD CONTROL 1 */
+#define S3C_WIN1MAP		S3C_LCDREG(0xD4)  	/* LCD CONTROL 1 */
+#define S3C_WPALCON		S3C_LCDREG(0xE4)  	/* LCD CONTROL 1 */
+#define S3C_SYSIFCON0		S3C_LCDREG(0x130)  	/* LCD CONTROL 1 */
+#define S3C_SYSIFCON1		S3C_LCDREG(0x134)  	/* LCD CONTROL 1 */
+#define S3C_DITHMODE		S3C_LCDREG(0x138)  	/* LCD CONTROL 1 */
+#define S3C_SIFCCON0		S3C_LCDREG(0x13C)  	/* LCD CONTROL 1 */
+#define S3C_SIFCCON1		S3C_LCDREG(0x140)  	/* LCD CONTROL 1 */
+#define S3C_SIFCCON2		S3C_LCDREG(0x144)  	/* LCD CONTROL 1 */
+#define S3C_CPUTRIGCON2		S3C_LCDREG(0x160)  	/* LCD CONTROL 1 */
+
+#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100)
+#define S3C_VIDCON2		S3C_LCDREG(0x08)  	/* Video control 2 register */
+#define S3C_VIDTCON0		S3C_LCDREG(0x10)  	/* Video time control 0 register */
+#define S3C_VIDTCON1		S3C_LCDREG(0x14)  	/* Video time control 1 register */
+#define S3C_VIDTCON2		S3C_LCDREG(0x18)  	/* Video time control 2 register */
+#define S3C_VIDTCON3		S3C_LCDREG(0x1C)  	/* Video time control 3 register */
+
+#define S3C_WINCON0		S3C_LCDREG(0x20)  	/* Window control 0 register */
+#define S3C_WINCON1		S3C_LCDREG(0x24)  	/* Window control 1 register */
+#define S3C_WINCON2		S3C_LCDREG(0x28)  	/* Window control 2 register */
+#define S3C_WINCON3		S3C_LCDREG(0x2C)  	/* Window control 3 register */
+#define S3C_WINCON4		S3C_LCDREG(0x30)  	/* Window control 4 register*/
+
+
+#define S3C_VIDOSD0A		S3C_LCDREG(0x40)  	/* Video Window 0 position control register */
+#define S3C_VIDOSD0B		S3C_LCDREG(0x44)  	/* Video Window 0 position control register1 */
+#define S3C_VIDOSD0C		S3C_LCDREG(0x48)  	/* Video Window 0 position control register */
+
+#define S3C_VIDOSD1A		S3C_LCDREG(0x50)  	/* Video Window 1 position control register */
+#define S3C_VIDOSD1B		S3C_LCDREG(0x54)  	/* Video Window 1 position control register */
+#define S3C_VIDOSD1C		S3C_LCDREG(0x58)  	/* Video Window 1 position control register */
+#define S3C_VIDOSD1D		S3C_LCDREG(0x5C)  	/* Video Window 1 position control register */
+
+#define S3C_VIDOSD2A		S3C_LCDREG(0x60)  	/* Video Window 2 position control register */
+#define S3C_VIDOSD2B		S3C_LCDREG(0x64)  	/* Video Window 2 position control register */
+#define S3C_VIDOSD2C		S3C_LCDREG(0x68)  	/* Video Window 2 position control register */
+#define S3C_VIDOSD2D		S3C_LCDREG(0x6C)  	/* Video Window 2 position control register */
+
+#define S3C_VIDOSD3A		S3C_LCDREG(0x70)  	/* Video Window 3 position control register */
+#define S3C_VIDOSD3B		S3C_LCDREG(0x74)  	/* Video Window 3 position control register */
+#define S3C_VIDOSD3C		S3C_LCDREG(0x78)  	/* Video Window 3 position control register */
+
+#define S3C_VIDOSD4A		S3C_LCDREG(0x80)  	/* Video Window 4 position control register */
+#define S3C_VIDOSD4B		S3C_LCDREG(0x84)  	/* Video Window 4 position control register */
+#define S3C_VIDOSD4C		S3C_LCDREG(0x88)  	/* Video Window 4 position control register */
+
+#define S3C_VIDW00ADD2B0	S3C_LCDREG(0x94)  	/* LCD CONTROL 1 */
+#define S3C_VIDW00ADD2B1	S3C_LCDREG(0x98)  	/* LCD CONTROL 1 */
+
+#define S3C_VIDW00ADD0B0	S3C_LCDREG(0x0A0) 	/* Window 0 buffer start address register, buffer 0 */
+#define S3C_VIDW00ADD0B1	S3C_LCDREG(0x0A4) 	/* Window 0 buffer start address register, buffer 1 */
+#define S3C_VIDW01ADD0B0	S3C_LCDREG(0x0A8) 	/* Window 1 buffer start address register, buffer 0 */
+#define S3C_VIDW01ADD0B1	S3C_LCDREG(0x0AC) 	/* Window 1 buffer start address register, buffer 1 */
+#define S3C_VIDW02ADD0		S3C_LCDREG(0x0B0) 	/* Window 2 buffer start address register */
+#define S3C_VIDW03ADD0		S3C_LCDREG(0x0B8) 	/* Window 3 buffer start address register */
+#define S3C_VIDW04ADD0		S3C_LCDREG(0x0C0) 	/* Window 4 buffer start address register */
+#define S3C_VIDW00ADD1B0	S3C_LCDREG(0x0D0) 	/* Window 0 buffer end address register, buffer 0 */
+#define S3C_VIDW00ADD1B1	S3C_LCDREG(0x0D4) 	/* Window 0 buffer end address register, buffer 1 */
+#define S3C_VIDW01ADD1B0	S3C_LCDREG(0x0D8) 	/* Window 1 buffer end address register, buffer 0 */
+#define S3C_VIDW01ADD1B1	S3C_LCDREG(0x0DC) 	/* Window 1 buffer end address register, buffer 1 */
+#define S3C_VIDW02ADD1		S3C_LCDREG(0x0E0) 	/* Window 2 buffer end address register */
+#define S3C_VIDW03ADD1		S3C_LCDREG(0x0E8) 	/* Window 3 buffer end address register */
+#define S3C_VIDW04ADD1		S3C_LCDREG(0x0F0) 	/* Window 4 buffer end address register */
+#define S3C_VIDW00ADD2		S3C_LCDREG(0x100) 	/* Window 0 buffer size register */
+#define S3C_VIDW01ADD2		S3C_LCDREG(0x104) 	/* Window 1 buffer size register */
+
+#define S3C_VIDW02ADD2		S3C_LCDREG(0x108) 	/* Window 2 buffer size register */
+#define S3C_VIDW03ADD2		S3C_LCDREG(0x10C) 	/* Window 3 buffer size register */
+#define S3C_VIDW04ADD2		S3C_LCDREG(0x110) 	/* Window 4 buffer size register */
+
+#define S3C_VIDINTCON0		S3C_LCDREG(0x130)	/* Indicate the Video interrupt control register */
+#define S3C_VIDINTCON1		S3C_LCDREG(0x134) 	/* Video Interrupt Pending register */
+#define S3C_W1KEYCON0		S3C_LCDREG(0x140) 	/* Color key control register */
+#define S3C_W1KEYCON1		S3C_LCDREG(0x144) 	/* Color key value ( transparent value) register */
+#define S3C_W2KEYCON0		S3C_LCDREG(0x148) 	/* Color key control register */
+#define S3C_W2KEYCON1		S3C_LCDREG(0x14C) 	/* Color key value (transparent value) register */
+
+#define S3C_W3KEYCON0		S3C_LCDREG(0x150)	/* Color key control register	*/
+#define S3C_W3KEYCON1		S3C_LCDREG(0x154)	/* Color key value (transparent value) register	*/
+#define S3C_W4KEYCON0		S3C_LCDREG(0x158)	/* Color key control register	*/
+#define S3C_W4KEYCON1		S3C_LCDREG(0x15C)	/* Color key value (transparent value) register	*/
+#define S3C_DITHMODE		S3C_LCDREG(0x170)	/* Dithering mode register.	*/
+
+#define S3C_WIN0MAP		S3C_LCDREG(0x180)	/* Window color control	*/
+#define S3C_WIN1MAP		S3C_LCDREG(0x184)	/* Window color control	*/
+#define S3C_WIN2MAP		S3C_LCDREG(0x188)	/* Window color control	*/
+#define S3C_WIN3MAP		S3C_LCDREG(0x18C)	/* Window color control	*/
+#define S3C_WIN4MAP		S3C_LCDREG(0x190)	/* Window color control	*/
+#define S3C_WPALCON		S3C_LCDREG(0x1A0)	/* Window Palette control register	*/
+
+#define S3C_TRIGCON		S3C_LCDREG(0x1A4)	/* I80 / RGB Trigger Control Regiter	*/
+#define S3C_I80IFCONA0		S3C_LCDREG(0x1B0)	/* I80 Interface control 0 for Main LDI	*/
+#define S3C_I80IFCONA1		S3C_LCDREG(0x1B4)	/* I80 Interface control 0 for Sub LDI	*/
+#define S3C_I80IFCONB0		S3C_LCDREG(0x1B8)	/* I80 Inteface control 1 for Main LDI	*/
+#define S3C_I80IFCONB1		S3C_LCDREG(0x1BC)	/* I80 Inteface control 1 for Sub LDI	*/
+#define S3C_LDI_CMDCON0		S3C_LCDREG(0x1D0)	/* I80 Interface LDI Command Control 0	*/
+#define S3C_LDI_CMDCON1		S3C_LCDREG(0x1D4)	/* I80 Interface LDI Command Control 1	*/
+#define S3C_SIFCCON0		S3C_LCDREG(0x1E0)	/* LCD i80 System Interface Command Control 0	*/
+#define S3C_SIFCCON1		S3C_LCDREG(0x1E4)	/* LCD i80 System Interface Command Control 1	*/
+#define S3C_SIFCCON2		S3C_LCDREG(0x1E8)	/* LCD i80 System Interface Command Control 2	*/
+
+#define S3C_LDI_CMD0		S3C_LCDREG(0x280)	/* I80 Inteface LDI Command 0	*/
+#define S3C_LDI_CMD1		S3C_LCDREG(0x284)	/* I80 Inteface LDI Command 1	*/
+#define S3C_LDI_CMD2		S3C_LCDREG(0x288)	/* I80 Inteface LDI Command 2	*/
+#define S3C_LDI_CMD3		S3C_LCDREG(0x28C)	/* I80 Inteface LDI Command 3	*/
+#define S3C_LDI_CMD4		S3C_LCDREG(0x290)	/* I80 Inteface LDI Command 4	*/
+#define S3C_LDI_CMD5		S3C_LCDREG(0x294)	/* I80 Inteface LDI Command 5	*/
+#define S3C_LDI_CMD6		S3C_LCDREG(0x298)	/* I80 Inteface LDI Command 6	*/
+#define S3C_LDI_CMD7		S3C_LCDREG(0x29C)	/* I80 Inteface LDI Command 7	*/
+#define S3C_LDI_CMD8		S3C_LCDREG(0x2A0)	/* I80 Inteface LDI Command 8	*/
+#define S3C_LDI_CMD9		S3C_LCDREG(0x2A4)	/* I80 Inteface LDI Command 9	*/
+#define S3C_LDI_CMD10		S3C_LCDREG(0x2A8)	/* I80 Inteface LDI Command 10	*/
+#define S3C_LDI_CMD11		S3C_LCDREG(0x2AC)	/* I80 Inteface LDI Command 11	*/
+
+#define S3C_W2PDATA01		S3C_LCDREG(0x300)	/* Window 2 Palette Data of the Index 0,1	*/
+#define S3C_W2PDATA23		S3C_LCDREG(0x304)	/* Window 2 Palette Data of the Index 2,3	*/
+#define S3C_W2PDATA45		S3C_LCDREG(0x308)	/* Window 2 Palette Data of the Index 4,5	*/
+#define S3C_W2PDATA67		S3C_LCDREG(0x30C)	/* Window 2 Palette Data of the Index 6,7	*/
+#define S3C_W2PDATA89		S3C_LCDREG(0x310)	/* Window 2 Palette Data of the Index 8,9	*/
+#define S3C_W2PDATAAB		S3C_LCDREG(0x314)	/* Window 2 Palette Data of the Index A, B	*/
+#define S3C_W2PDATACD		S3C_LCDREG(0x318)	/* Window 2 Palette Data of the Index C, D	*/
+#define S3C_W2PDATAEF		S3C_LCDREG(0x31C)	/* Window 2 Palette Data of the Index E, F	*/
+#define S3C_W3PDATA01		S3C_LCDREG(0x320)	/* Window 3 Palette Data of the Index 0,1	*/
+#define S3C_W3PDATA23		S3C_LCDREG(0x324)	/* Window 3 Palette Data of the Index 2,3	*/
+#define S3C_W3PDATA45		S3C_LCDREG(0x328)	/* Window 3 Palette Data of the Index 4,5	*/
+#define S3C_W3PDATA67		S3C_LCDREG(0x32C)	/* Window 3 Palette Data of the Index 6,7	*/
+#define S3C_W3PDATA89		S3C_LCDREG(0x330)	/* Window 3 Palette Data of the Index 8,9	*/
+#define S3C_W3PDATAAB		S3C_LCDREG(0x334)	/* Window 3 Palette Data of the Index A, B	*/
+#define S3C_W3PDATACD		S3C_LCDREG(0x338)	/* Window 3 Palette Data of the Index C, D	*/
+#define S3C_W3PDATAEF		S3C_LCDREG(0x33C)	/* Window 3 Palette Data of the Index E, F	*/
+#define S3C_W4PDATA01		S3C_LCDREG(0x340)	/* Window 3 Palette Data of the Index 0,1	*/
+#define S3C_W4PDATA23		S3C_LCDREG(0x344)	/* Window 3 Palette Data of the Index 2,3	*/
+#endif
+
+#define S3C_TFTPAL2(x)		S3C_LCDREG((0x300 + (x)*4))
+#define S3C_TFTPAL3(x) 		S3C_LCDREG((0x320 + (x)*4))
+#define S3C_TFTPAL4(x)		S3C_LCDREG((0x340 + (x)*4))
+#define S3C_TFTPAL0(x)		S3C_LCDREG((0x400 + (x)*4))
+#define S3C_TFTPAL1(x)		S3C_LCDREG((0x800 + (x)*4))
+
+/*--------------------------------------------------------------*/
+/* Video Main Control 0 register - VIDCON0 */
+#define S3C_VIDCON0_INTERLACE_F_PROGRESSIVE		(0<<29)
+#define S3C_VIDCON0_INTERLACE_F_INTERLACE		(1<<29)
+#define S3C_VIDCON0_VIDOUT(x)  				(((x)&0x7)<<26)
+#define S3C_VIDCON0_VIDOUT_RGB_IF			(0<<26)
+#define S3C_VIDCON0_VIDOUT_TV				(1<<26)
+#define S3C_VIDCON0_VIDOUT_I80IF0			(2<<26)
+#define S3C_VIDCON0_VIDOUT_I80IF1			(3<<26)
+#define S3C_VIDCON0_VIDOUT_TVNRGBIF 			(4<<26)
+#define S3C_VIDCON0_VIDOUT_TVNI80IF0			(6<<26)
+#define S3C_VIDCON0_VIDOUT_TVNI80IF1			(7<<26)
+#define S3C_VIDCON0_L1_DATA16(x)  			(((x)&0x7)<<23)
+#define S3C_VIDCON0_L1_DATA16_SUB_16_MODE		(0<<23)
+#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE		(1<<23)
+#define S3C_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE 		(2<<23)
+#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE		(3<<23)
+#define S3C_VIDCON0_L1_DATA16_SUB_18_MODE		(4<<23)
+#define S3C_VIDCON0_L0_DATA16(x)  			(((x)&0x7)<<20)
+#define S3C_VIDCON0_L0_DATA16_MAIN_16_MODE		(0<<20)
+#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE		(1<<20)
+#define S3C_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE		(2<<20)
+#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE		(3<<20)
+#define S3C_VIDCON0_L0_DATA16_MAIN_18_MODE		(4<<20)
+#define S3C_VIDCON0_PNRMODE(x)  			(((x)&0x3)<<17)
+#define S3C_VIDCON0_PNRMODE_RGB_P			(0<<17)
+#define S3C_VIDCON0_PNRMODE_BGR_P			(1<<17)
+#define S3C_VIDCON0_PNRMODE_RGB_S			(2<<17)
+#define S3C_VIDCON0_PNRMODE_BGR_S			(3<<17)
+#define S3C_VIDCON0_PNRMODE_MASK			(3<<17)
+#define S3C_VIDCON0_CLKVALUP_ALWAYS 			(0<<16)
+#define S3C_VIDCON0_CLKVALUP_ST_FRM 			(1<<16)
+#define S3C_VIDCON0_CLKVAL_F(x)				(((x)&0xFF)<<6)
+#define S3C_VIDCON0_VCLKEN_ENABLE			(1<<5)
+#define S3C_VIDCON0_CLKDIR_DIVIDED   			(1<<4)
+#define S3C_VIDCON0_CLKDIR_DIRECTED  			(0<<4)
+#define S3C_VIDCON0_CLKSEL(x)   			(((x)&0x3)<<2)
+#define S3C_VIDCON0_CLKSEL_F_HCLK	  		(0<<2)
+#define S3C_VIDCON0_ENVID_ENABLE	    		(1 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
+#define S3C_VIDCON0_ENVID_DISABLE	    		(0 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
+#define S3C_VIDCON0_ENVID_F_ENABLE     			(1 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */
+#define S3C_VIDCON0_ENVID_F_DISABLE     		(0 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */
+
+/* Video Main Control 1 register - VIDCON1 */
+#define S3C_VIDCON1_IVCLK_FALL_EDGE 			(0<<7)
+#define S3C_VIDCON1_IVCLK_RISE_EDGE 			(1<<7)
+#define S3C_VIDCON1_IHSYNC_NORMAL			(0<<6)
+#define S3C_VIDCON1_IHSYNC_INVERT			(1<<6)
+#define S3C_VIDCON1_IVSYNC_NORMAL			(0<<5)
+#define S3C_VIDCON1_IVSYNC_INVERT			(1<<5)
+#define S3C_VIDCON1_IVDEN_NORMAL			(0<<4)
+#define S3C_VIDCON1_IVDEN_INVERT			(1<<4)
+
+/* Video Main Control 2 register - VIDCON2 */
+#define S3C_VIDCON2_TVLFFORMAT(x)   			(((x)&0x7)<<7)
+
+/* VIDEO Time Control 0 register - VIDTCON0 */
+#define S3C_VIDTCON0_VBPDE(x)				(((x)&0xFF)<<24)
+#define S3C_VIDTCON0_VBPD(x)				(((x)&0xFF)<<16)
+#define S3C_VIDTCON0_VFPD(x) 				(((x)&0xFF)<<8)
+#define S3C_VIDTCON0_VSPW(x) 				(((x)&0xFF)<<0)
+
+/* VIDEO Time Control 1 register - VIDTCON1 */
+#define S3C_VIDTCON1_VFPDE(x)				(((x)&0xFF)<<24)
+#define S3C_VIDTCON1_HBPD(x) 				(((x)&0xFF)<<16)
+#define S3C_VIDTCON1_HFPD(x) 				(((x)&0xFF)<<8)
+#define S3C_VIDTCON1_HSPW(x) 				(((x)&0xFF)<<0)
+
+/* VIDEO Time Control 2 register - VIDTCON2 */
+#define S3C_VIDTCON2_LINEVAL(x)  			(((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */
+#define S3C_VIDTCON2_HOZVAL(x)   			(((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/
+
+
+/* Window 0~4 Control register - WINCONx */
+#define S3C_WINCONx_WIDE_NARROW(x)			(((x)&0x3)<<26)
+#define S3C_WINCONx_ENLOCAL_DMA				(0<<22)
+#define S3C_WINCONx_ENLOCAL_POST			(1<<22)
+#define S3C_WINCONx_BUFSEL_0				(0<<20)
+#define S3C_WINCONx_BUFSEL_1				(1<<20)
+#define S3C_WINCONx_BUF_MASK				(1<<20)
+#define S3C_WINCONx_BUFAUTOEN_DISABLE			(0<<19)
+#define S3C_WINCONx_BUFAUTOEN_ENABLE			(1<<19)
+#define S3C_WINCONx_BUFAUTOEN_MASK			(1<<19)
+#define S3C_WINCONx_BITSWP_DISABLE			(0<<18)
+#define S3C_WINCONx_BITSWP_ENABLE			(1<<18)
+#define S3C_WINCONx_BYTSWP_DISABLE			(0<<17)
+#define S3C_WINCONx_BYTSWP_ENABLE			(1<<17)
+#define S3C_WINCONx_HAWSWP_DISABLE			(0<<16)
+#define S3C_WINCONx_HAWSWP_ENABLE			(1<<16)
+#define S3C_WINCONx_INRGB_RGB		   		(0<<13)
+#define S3C_WINCONx_INRGB_YUV		 		(1<<13)
+#define S3C_WINCONx_INRGB_MASK				(1<<13)
+#define S3C_WINCONx_BURSTLEN_16WORD			(0<<9)
+#define S3C_WINCONx_BURSTLEN_8WORD			(1<<9)
+#define S3C_WINCONx_BURSTLEN_4WORD			(2<<9)
+#define S3C_WINCONx_BLD_PIX_PLANE			(0<<6)
+#define S3C_WINCONx_BLD_PIX_PIXEL			(1<<6)
+#define S3C_WINCONx_BLD_PIX_MASK			(1<<6)
+#define S3C_WINCONx_BPPMODE_F_1BPP			(0<<2)
+#define S3C_WINCONx_BPPMODE_F_2BPP			(1<<2)
+#define S3C_WINCONx_BPPMODE_F_4BPP			(2<<2)
+#define S3C_WINCONx_BPPMODE_F_8BPP_PAL			(3<<2)
+#define S3C_WINCONx_BPPMODE_F_8BPP_NOPAL		(4<<2)
+#define S3C_WINCONx_BPPMODE_F_16BPP_565			(5<<2)
+#define S3C_WINCONx_BPPMODE_F_16BPP_A555		(6<<2)
+#define S3C_WINCONx_BPPMODE_F_18BPP_666			(8<<2)
+#define S3C_WINCONx_BPPMODE_F_24BPP_888			(11<<2)
+#define S3C_WINCONx_BPPMODE_F_24BPP_A887		(0xc<<2)
+#define S3C_WINCONx_BPPMODE_F_25BPP_A888		(0xd<<2)
+#define S3C_WINCONx_BPPMODE_F_28BPP_A888		(0xd<<2)
+#define S3C_WINCONx_BPPMODE_F_MASK			(0xf<<2)
+#define S3C_WINCONx_ALPHA_SEL_0				(0<<1)
+#define S3C_WINCONx_ALPHA_SEL_1				(1<<1)
+#define S3C_WINCONx_ALPHA_SEL_MASK			(1<<1)
+#define S3C_WINCONx_ENWIN_F_DISABLE 			(0<<0)
+#define S3C_WINCONx_ENWIN_F_ENABLE			(1<<0)
+
+/* Window 1-2 Control register - WINCON1 */
+#define S3C_WINCON1_LOCALSEL_TV				(0<<23)
+#define S3C_WINCON1_LOCALSEL_CAMERA			(1<<23)
+#define S3C_WINCON2_LOCALSEL_TV				(0<<23)
+#define S3C_WINCON2_LOCALSEL_CAMERA			(1<<23)
+
+/* Window 0~4 Position Control A register - VIDOSDxA */
+#define S3C_VIDOSDxA_OSD_LTX_F(x)			(((x)&0x7FF)<<11)
+#define S3C_VIDOSDxA_OSD_LTY_F(x)			(((x)&0x7FF)<<0)
+
+/* Window 0~4 Position Control B register - VIDOSDxB */
+#define S3C_VIDOSDxB_OSD_RBX_F(x)			(((x)&0x7FF)<<11)
+#define S3C_VIDOSDxB_OSD_RBY_F(x)			(((x)&0x7FF)<<0)
+
+/* Window 0 Position Control C register - VIDOSD0C */
+#define  S3C_VIDOSD0C_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)
+
+/* Window 1~4 Position Control C register - VIDOSDxC */
+#define S3C_VIDOSDxC_ALPHA0_R(x)			(((x)&0xF)<<20)
+#define S3C_VIDOSDxC_ALPHA0_G(x)			(((x)&0xF)<<16)
+#define S3C_VIDOSDxC_ALPHA0_B(x)			(((x)&0xF)<<12)
+#define S3C_VIDOSDxC_ALPHA1_R(x)			(((x)&0xF)<<8)
+#define S3C_VIDOSDxC_ALPHA1_G(x)			(((x)&0xF)<<4)
+#define S3C_VIDOSDxC_ALPHA1_B(x)			(((x)&0xF)<<0)
+
+/* Window 1~2 Position Control D register - VIDOSDxD */
+#define  S3C_VIDOSDxD_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)
+
+/* Frame buffer Start Address register - VIDWxxADD0 */
+#define S3C_VIDWxxADD0_VBANK_F(x) 			(((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */
+#define S3C_VIDWxxADD0_VBASEU_F(x)			(((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */
+
+/* Frame buffer End Address register - VIDWxxADD1 */
+#define S3C_VIDWxxADD1_VBASEL_F(x) 			(((x)&0xFFFFFF)<<0)  /* the end address of the LCD frame buffer. */
+
+/* Frame buffer Size register - VIDWxxADD2 */
+#define S3C_VIDWxxADD2_OFFSIZE_F(x)  			(((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */
+#define S3C_VIDWxxADD2_PAGEWIDTH_F(x)			(((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */
+
+/* VIDEO Interrupt Control 0 register - VIDINTCON0 */
+#define S3C_VIDINTCON0_FIFOINTERVAL(x)			(((x)&0x3F)<<20)
+#define S3C_VIDINTCON0_SYSMAINCON_DISABLE		(0<<19)
+#define S3C_VIDINTCON0_SYSMAINCON_ENABLE		(1<<19)
+#define S3C_VIDINTCON0_SYSSUBCON_DISABLE		(0<<18)
+#define S3C_VIDINTCON0_SYSSUBCON_ENABLE			(1<<18)
+#define S3C_VIDINTCON0_SYSIFDONE_DISABLE		(0<<17)
+#define S3C_VIDINTCON0_SYSIFDONE_ENABLE			(1<<17)
+#define S3C_VIDINTCON0_FRAMESEL0_BACK			(0<<15)
+#define S3C_VIDINTCON0_FRAMESEL0_VSYNC 			(1<<15)
+#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE			(2<<15)
+#define S3C_VIDINTCON0_FRAMESEL0_FRONT 			(3<<15)
+#define S3C_VIDINTCON0_FRAMESEL0_MASK 			(3<<15)
+#define S3C_VIDINTCON0_FRAMESEL1_NONE			(0<<13)
+#define S3C_VIDINTCON0_FRAMESEL1_BACK			(1<<13)
+#define S3C_VIDINTCON0_FRAMESEL1_VSYNC 			(2<<13)
+#define S3C_VIDINTCON0_FRAMESEL1_FRONT 			(3<<13)
+#define S3C_VIDINTCON0_INTFRMEN_DISABLE			(0<<12)
+#define S3C_VIDINTCON0_INTFRMEN_ENABLE 			(1<<12)
+#define S3C_VIDINTCON0_FRAMEINT_MASK			(0x1F<<12)
+#define S3C_VIDINTCON0_FIFOSEL_WIN4			(1<<11)
+#define S3C_VIDINTCON0_FIFOSEL_WIN3			(1<<10)
+#define S3C_VIDINTCON0_FIFOSEL_WIN2			(1<<9)
+#define S3C_VIDINTCON0_FIFOSEL_WIN1			(1<<6)
+#define S3C_VIDINTCON0_FIFOSEL_WIN0			(1<<5)
+#define S3C_VIDINTCON0_FIFOSEL_ALL			(0x73<<5)
+#define S3C_VIDINTCON0_FIFOLEVEL_25			(0<<2)
+#define S3C_VIDINTCON0_FIFOLEVEL_50			(1<<2)
+#define S3C_VIDINTCON0_FIFOLEVEL_75			(2<<2)
+#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY 			(3<<2)
+#define S3C_VIDINTCON0_FIFOLEVEL_FULL			(4<<2)
+#define S3C_VIDINTCON0_INTFIFOEN_DISABLE		(0<<1)
+#define S3C_VIDINTCON0_INTFIFOEN_ENABLE			(1<<1)
+#define S3C_VIDINTCON0_INTEN_DISABLE			(0<<0)
+#define S3C_VIDINTCON0_INTEN_ENABLE			(1<<0)
+#define S3C_VIDINTCON0_INTEN_MASK			(1<<0)
+
+/* VIDEO Interrupt Control 1 register - VIDINTCON1 */
+#define S3C_VIDINTCON1_INTI80PEND			(0<<2)
+#define S3C_VIDINTCON1_INTFRMPEND			(1<<1)
+#define S3C_VIDINTCON1_INTFIFOPEND			(1<<0)
+
+/* WIN 1~4 Color Key 0 register - WxKEYCON0 */
+#define S3C_WxKEYCON0_KEYBLEN_DISABLE 			(0<<26)
+#define S3C_WxKEYCON0_KEYBLEN_ENABLE			(1<<26)
+#define S3C_WxKEYCON0_KEYEN_F_DISABLE 			(0<<25)
+#define S3C_WxKEYCON0_KEYEN_F_ENABLE			(1<<25)
+#define S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE		(0<<24)
+#define S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE		(1<<24)
+#define S3C_WxKEYCON0_COMPKEY(x)			(((x)&0xFFFFFF)<<0)
+
+/* WIN 1~4 Color Key 1 register - WxKEYCON1 */
+#define S3C_WxKEYCON1_COLVAL(x)				(((x)&0xFFFFFF)<<0)
+
+/* Dithering Control 1 register - DITHMODE */
+#define S3C_DITHMODE_RDITHPOS_8BIT			(0<<5)
+#define S3C_DITHMODE_RDITHPOS_6BIT			(1<<5)
+#define S3C_DITHMODE_RDITHPOS_5BIT			(2<<5)
+#define S3C_DITHMODE_GDITHPOS_8BIT			(0<<3)
+#define S3C_DITHMODE_GDITHPOS_6BIT			(1<<3)
+#define S3C_DITHMODE_GDITHPOS_5BIT			(2<<3)
+#define S3C_DITHMODE_BDITHPOS_8BIT			(0<<1)
+#define S3C_DITHMODE_BDITHPOS_6BIT			(1<<1)
+#define S3C_DITHMODE_BDITHPOS_5BIT			(2<<1)
+#define S3C_DITHMODE_RGB_DITHPOS_MASK			(0x3f<<1)
+#define S3C_DITHMODE_DITHERING_DISABLE			(0<<0)
+#define S3C_DITHMODE_DITHERING_ENABLE			(1<<0)
+#define S3C_DITHMODE_DITHERING_MASK			(1<<0)
+
+/* Window 0~4 Color map register - WINxMAP */
+#define S3C_WINxMAP_MAPCOLEN_F_ENABLE			(1<<24)
+#define S3C_WINxMAP_MAPCOLEN_F_DISABLE			(0<<24)
+#define S3C_WINxMAP_MAPCOLOR				(((x)&0xFFFFFF)<<0)
+
+/* Window Palette Control register - WPALCON */
+#define S3C_WPALCON_PALUPDATEEN				(1<<9)
+#define S3C_WPALCON_W4PAL_16BIT_A	 		(1<<8)		/* A:5:5:5 */
+#define S3C_WPALCON_W4PAL_16BIT	 			(0<<8)		/*  5:6:5 */
+#define S3C_WPALCON_W3PAL_16BIT_A	 		(1<<7)		/* A:5:5:5 */
+#define S3C_WPALCON_W3PAL_16BIT	 			(0<<7)		/*  5:6:5 */
+#define S3C_WPALCON_W2PAL_16BIT_A	 		(1<<6)		/* A:5:5:5 */
+#define S3C_WPALCON_W2PAL_16BIT	 			(0<<6)		/*  5:6:5 */
+#define S3C_WPALCON_W1PAL_25BIT_A	 		(0<<3)		/* A:8:8:8 */
+#define S3C_WPALCON_W1PAL_24BIT				(1<<3)		/*  8:8:8 */
+#define S3C_WPALCON_W1PAL_19BIT_A			(2<<3)		/* A:6:6:6 */
+#define S3C_WPALCON_W1PAL_18BIT_A	 		(3<<3)		/* A:6:6:5 */
+#define S3C_WPALCON_W1PAL_18BIT				(4<<3)		/*  6:6:6 */
+#define S3C_WPALCON_W1PAL_16BIT_A	 		(5<<3)		/* A:5:5:5 */
+#define S3C_WPALCON_W1PAL_16BIT	 			(6<<3)		/*  5:6:5 */
+#define S3C_WPALCON_W0PAL_25BIT_A	 		(0<<0)		/* A:8:8:8 */
+#define S3C_WPALCON_W0PAL_24BIT				(1<<0)		/*  8:8:8 */
+#define S3C_WPALCON_W0PAL_19BIT_A			(2<<0)		/* A:6:6:6 */
+#define S3C_WPALCON_W0PAL_18BIT_A	 		(3<<0)		/* A:6:6:5 */
+#define S3C_WPALCON_W0PAL_18BIT				(4<<0)		/*  6:6:6 */
+#define S3C_WPALCON_W0PAL_16BIT_A	 		(5<<0)		/* A:5:5:5 */
+#define S3C_WPALCON_W0PAL_16BIT	 			(6<<0)		/*  5:6:5 */
+
+/* I80/RGB Trigger Control register - TRIGCON */
+#define S3C_TRIGCON_SWFRSTATUS_REQUESTED		(1<<2)
+#define S3C_TRIGCON_SWFRSTATUS_NOT_REQUESTED		(0<<2)
+#define S3C_TRIGCON_SWTRGCMD				(1<<1)
+#define S3C_TRIGCON_TRGMODE_ENABLE			(1<<0)
+#define S3C_TRIGCON_TRGMODE_DISABLE			(0<<0)
+
+/* LCD I80 Interface Control 0 register - I80IFCONA0 */
+#define S3C_I80IFCONAx_LCD_CS_SETUP(x) 			(((x)&0xF)<<16)
+#define S3C_I80IFCONAx_LCD_WR_SETUP(x) 			(((x)&0xF)<<12)
+#define S3C_I80IFCONAx_LCD_WR_ACT(x)			(((x)&0xF)<<8)
+#define S3C_I80IFCONAx_LCD_WR_HOLD(x)			(((x)&0xF)<<4)
+
+
+/***************************************************************************/
+/*HOST IF registers */
+/* Host I/F A - */
+#define S3C_HOSTIFAREG(x)				((x) + S3C64XX_VA_HOSTIFA)
+#define S3C_HOSTIFAREG_PHYS(x)				((x) + S3C64XX_PA_HOSTIFA)
+
+/* Host I/F B - Modem I/F */
+#define S3C_HOSTIFBREG(x)				((x) + S3C64XX_VA_HOSTIFB)
+#define S3C_HOSTIFBREG_PHYS(x)				((x) + S3C64XX_PA_HOSTIFB)
+
+#define S3C_HOSTIFB_INT2AP				S3C_HOSTIFBREG(0x8000)
+#define S3C_HOSTIFB_INT2MSM				S3C_HOSTIFBREG(0x8004)
+#define S3C_HOSTIFB_MIFCON				S3C_HOSTIFBREG(0x8008)
+#define S3C_HOSTIFB_MIFPCON				S3C_HOSTIFBREG(0x800C)
+#define S3C_HOSTIFB_MSMINTCLR				S3C_HOSTIFBREG(0x8010)
+
+#define S3C_HOSTIFB_MIFCON_INT2MSM_DIS			(0x0<<3)
+#define S3C_HOSTIFB_MIFCON_INT2MSM_EN			(0x1<<3)
+#define S3C_HOSTIFB_MIFCON_INT2AP_DIS			(0x0<<2)
+#define S3C_HOSTIFB_MIFCON_INT2AP_EN			(0x1<<2)
+#define S3C_HOSTIFB_MIFCON_WAKEUP_DIS			(0x0<<1)
+#define S3C_HOSTIFB_MIFCON_WAKEUP_EN			(0x1<<1)
+
+#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT		(0x0<<5)
+#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN		(0x1<<5)
+#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS		(0x0<<4)
+#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_EN		(0x1<<4)
+#define S3C_HOSTIFB_MIFPCON_SEL_NORMAL			(0x0<<3)
+#define S3C_HOSTIFB_MIFPCON_SEL_BYPASS			(0x1<<3)
+
+#define S3C_HOSTIFB_MIFPCON_SEL_RS0			0
+#define S3C_HOSTIFB_MIFPCON_SEL_RS1			1
+#define S3C_HOSTIFB_MIFPCON_SEL_RS2			2
+#define S3C_HOSTIFB_MIFPCON_SEL_RS3			3
+#define S3C_HOSTIFB_MIFPCON_SEL_RS4			4
+#define S3C_HOSTIFB_MIFPCON_SEL_RS5			5
+#define S3C_HOSTIFB_MIFPCON_SEL_RS6			6
+
+#endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-nand.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-nand.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-nand.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-nand.h	2009-04-10 11:22:31.000000000 +0900
@@ -117,7 +117,56 @@
 #define S3C2412_NFECCERR_MULTIBIT	(2)
 #define S3C2412_NFECCERR_ECCAREA	(3)
 
+/* for s3c_nand.c */
+#define S3C_NFCONF		S3C2410_NFREG(0x00)
+#define S3C_NFCONT		S3C2410_NFREG(0x04)
+#define S3C_NFCMMD		S3C2410_NFREG(0x08)
+#define S3C_NFADDR		S3C2410_NFREG(0x0c)
+#define S3C_NFDATA8		S3C2410_NFREG(0x10)
+#define S3C_NFDATA		S3C2410_NFREG(0x10)
+#define S3C_NFMECCDATA0		S3C2410_NFREG(0x14)
+#define S3C_NFMECCDATA1		S3C2410_NFREG(0x18)
+#define S3C_NFSECCDATA		S3C2410_NFREG(0x1c)
+#define S3C_NFSBLK		S3C2410_NFREG(0x20)
+#define S3C_NFEBLK		S3C2410_NFREG(0x24)
+#define S3C_NFSTAT		S3C2410_NFREG(0x28)
+#define S3C_NFMECCERR0		S3C2410_NFREG(0x2c)
+#define S3C_NFMECCERR1		S3C2410_NFREG(0x30)
+#define S3C_NFMECC0		S3C2410_NFREG(0x34)
+#define S3C_NFMECC1		S3C2410_NFREG(0x38)
+#define S3C_NFSECC		S3C2410_NFREG(0x3c)
+#define S3C_NFMLCBITPT		S3C2410_NFREG(0x40)
 
+#define S3C_NFCONF_NANDBOOT	(1<<31)
+#define S3C_NFCONF_ECCCLKCON	(1<<30)
+#define S3C_NFCONF_ECC_MLC	(1<<24)
+#define	S3C_NFCONF_ECC_1BIT	(0<<23)
+#define	S3C_NFCONF_ECC_4BIT	(2<<23)
+#define	S3C_NFCONF_ECC_8BIT	(1<<23)
+#define S3C_NFCONF_TACLS(x)	((x)<<12)
+#define S3C_NFCONF_TWRPH0(x)	((x)<<8)
+#define S3C_NFCONF_TWRPH1(x)	((x)<<4)
+#define S3C_NFCONF_ADVFLASH	(1<<3)
+#define S3C_NFCONF_PAGESIZE	(1<<2)
+#define S3C_NFCONF_ADDRCYCLE	(1<<1)
+#define S3C_NFCONF_BUSWIDTH	(1<<0)
+
+#define S3C_NFCONT_ECC_ENC	(1<<18)
+#define S3C_NFCONT_LOCKTGHT	(1<<17)
+#define S3C_NFCONT_LOCKSOFT	(1<<16)
+#define S3C_NFCONT_MECCLOCK	(1<<7)
+#define S3C_NFCONT_SECCLOCK	(1<<6)
+#define S3C_NFCONT_INITMECC	(1<<5)
+#define S3C_NFCONT_INITSECC	(1<<4)
+#define S3C_NFCONT_nFCE1	(1<<2)
+#define S3C_NFCONT_nFCE0	(1<<1)
+#define S3C_NFCONT_INITECC	(S3C_NFCONT_INITSECC | S3C_NFCONT_INITMECC)
+
+#define S3C_NFSTAT_ECCENCDONE	(1<<7)
+#define S3C_NFSTAT_ECCDECDONE	(1<<6)
+#define S3C_NFSTAT_BUSY		(1<<0)
+
+#define S3C_NFECCERR0_ECCBUSY	(1<<31)
 
 #endif /* __ASM_ARM_REGS_NAND */
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,75 @@
+/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
+ *
+ * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
+#define __ASM_ARCH_REGS_S3C2412_IIS_H
+
+#define S3C2412_IISCON			(0x00)
+#define S3C2412_IISMOD			(0x04)
+#define S3C2412_IISFIC			(0x08)
+#define S3C2412_IISPSR			(0x0C)
+#define S3C2412_IISTXD			(0x10)
+#define S3C2412_IISRXD			(0x14)
+
+#define S3C2412_IISCON_LRINDEX		(1 << 11)
+#define S3C2412_IISCON_TXFIFO_EMPTY	(1 << 10)
+#define S3C2412_IISCON_RXFIFO_EMPTY	(1 << 9)
+#define S3C2412_IISCON_TXFIFO_FULL	(1 << 8)
+#define S3C2412_IISCON_RXFIFO_FULL	(1 << 7)
+#define S3C2412_IISCON_TXDMA_PAUSE	(1 << 6)
+#define S3C2412_IISCON_RXDMA_PAUSE	(1 << 5)
+#define S3C2412_IISCON_TXCH_PAUSE	(1 << 4)
+#define S3C2412_IISCON_RXCH_PAUSE	(1 << 3)
+#define S3C2412_IISCON_TXDMA_ACTIVE	(1 << 2)
+#define S3C2412_IISCON_RXDMA_ACTIVE	(1 << 1)
+#define S3C2412_IISCON_IIS_ACTIVE	(1 << 0)
+
+#define S3C64XX_IISMOD_IMS_PCLK		(0 << 10)
+#define S3C64XX_IISMOD_IMS_SYSMUX	(1 << 10)
+
+#define S3C2412_IISMOD_MASTER_INTERNAL	(0 << 10)
+#define S3C2412_IISMOD_MASTER_EXTERNAL	(1 << 10)
+#define S3C2412_IISMOD_SLAVE		(2 << 10)
+#define S3C2412_IISMOD_MASTER_MASK	(3 << 10)
+#define S3C2412_IISMOD_MODE_TXONLY	(0 << 8)
+#define S3C2412_IISMOD_MODE_RXONLY	(1 << 8)
+#define S3C2412_IISMOD_MODE_TXRX	(2 << 8)
+#define S3C2412_IISMOD_MODE_MASK	(3 << 8)
+#define S3C2412_IISMOD_LR_LLOW		(0 << 7)
+#define S3C2412_IISMOD_LR_RLOW		(1 << 7)
+#define S3C2412_IISMOD_SDF_IIS		(0 << 5)
+#define S3C2412_IISMOD_SDF_MSB		(1 << 5)
+#define S3C2412_IISMOD_SDF_LSB		(2 << 5)
+#define S3C2412_IISMOD_SDF_MASK		(3 << 5)
+#define S3C2412_IISMOD_RCLK_256FS	(0 << 3)
+#define S3C2412_IISMOD_RCLK_512FS	(1 << 3)
+#define S3C2412_IISMOD_RCLK_384FS	(2 << 3)
+#define S3C2412_IISMOD_RCLK_768FS	(3 << 3)
+#define S3C2412_IISMOD_RCLK_MASK 	(3 << 3)
+#define S3C2412_IISMOD_BCLK_32FS	(0 << 1)
+#define S3C2412_IISMOD_BCLK_48FS	(1 << 1)
+#define S3C2412_IISMOD_BCLK_16FS	(2 << 1)
+#define S3C2412_IISMOD_BCLK_24FS	(3 << 1)
+#define S3C2412_IISMOD_BCLK_MASK	(3 << 1)
+#define S3C2412_IISMOD_8BIT		(1 << 0)
+
+#define S3C2412_IISPSR_PSREN		(1 << 15)
+
+#define S3C2412_IISFIC_TXFLUSH		(1 << 15)
+#define S3C2412_IISFIC_RXFLUSH		(1 << 7)
+#define S3C2412_IISFIC_TXCOUNT(x)	(((x) >>  8) & 0xf)
+#define S3C2412_IISFIC_RXCOUNT(x)	(((x) >>  0) & 0xf)
+
+
+
+#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-serial.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-serial.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-serial.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-serial.h	2009-04-10 11:13:25.000000000 +0900
@@ -189,6 +189,11 @@
 
 #define S3C2443_DIVSLOT		  (0x2C)
 
+/* S3C64XX interrupt registers. */
+#define S3C64XX_UINTP		0x30
+#define S3C64XX_UINTSP		0x34
+#define S3C64XX_UINTM		0x38
+
 #ifndef __ASSEMBLY__
 
 /* struct s3c24xx_uart_clksrc
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-timer.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-timer.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-timer.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-timer.h	2009-04-10 11:13:25.000000000 +0900
@@ -10,6 +10,8 @@
  * S3C2410 Timer configuration
 */
 
+#include <plat/map-base.h>
+
 #ifndef __ASM_ARCH_REGS_TIMER_H
 #define __ASM_ARCH_REGS_TIMER_H
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-usb-hs-otg.h android_2.6.29/arch/arm/plat-s3c/include/plat/regs-usb-hs-otg.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/regs-usb-hs-otg.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/regs-usb-hs-otg.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,360 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
+ *
+ * Copyright (C) 2008 Samsung Electronics
+ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+*/
+
+#ifndef __ASM_ARCH_REGS_USB_HS_OTG_H
+#define __ASM_ARCH_REGS_USB_HS_OTG_H
+
+/* USB2.0 OTG Controller register */
+#define S3C_USBOTG_PHYREG(x)	((x) + 0x100000 /* S3C64XX_VA_OTGSFR */)
+#define S3C_USBOTG_PHYPWR		S3C_USBOTG_PHYREG(0x0)
+#define S3C_USBOTG_PHYCLK		S3C_USBOTG_PHYREG(0x4)
+#define S3C_USBOTG_RSTCON		S3C_USBOTG_PHYREG(0x8)
+
+/* USB2.0 OTG Controller register */
+/* Core Global Registers */
+#define S3C_USBOTGREG(x)		((x) /*+ S3C64XX_VA_OTG */)
+/* OTG Control & Status */
+#define S3C_UDC_OTG_GOTGCTL		S3C_USBOTGREG(0x000)
+/* OTG Interrupt */
+#define S3C_UDC_OTG_GOTGINT		S3C_USBOTGREG(0x004)
+/* Core AHB Configuration */
+#define S3C_UDC_OTG_GAHBCFG		S3C_USBOTGREG(0x008)
+/* Core USB Configuration */
+#define S3C_UDC_OTG_GUSBCFG		S3C_USBOTGREG(0x00C)
+/* Core Reset */
+#define S3C_UDC_OTG_GRSTCTL		S3C_USBOTGREG(0x010)
+/* Core Interrupt */
+#define S3C_UDC_OTG_GINTSTS		S3C_USBOTGREG(0x014)
+/* Core Interrupt Mask */
+#define S3C_UDC_OTG_GINTMSK		S3C_USBOTGREG(0x018)
+/* Receive Status Debug Read/Status Read */
+#define S3C_UDC_OTG_GRXSTSR		S3C_USBOTGREG(0x01C)
+/* Receive Status Debug Pop/Status Pop */
+#define S3C_UDC_OTG_GRXSTSP		S3C_USBOTGREG(0x020)
+/* Receive FIFO Size */
+#define S3C_UDC_OTG_GRXFSIZ		S3C_USBOTGREG(0x024)
+/* Non-Periodic Transmit FIFO Size */
+#define S3C_UDC_OTG_GNPTXFSIZ	S3C_USBOTGREG(0x028)
+/* Non-Periodic Transmit FIFO/Queue Status */
+#define S3C_UDC_OTG_GNPTXSTS	S3C_USBOTGREG(0x02C)
+
+/* Host Periodic Transmit FIFO Size */
+#define S3C_UDC_OTG_HPTXFSIZ	S3C_USBOTGREG(0x100)
+/* Device Periodic Transmit FIFO-1 Size */
+#define S3C_UDC_OTG_DPTXFSIZ1	S3C_USBOTGREG(0x104)
+/* Device Periodic Transmit FIFO-2 Size */
+#define S3C_UDC_OTG_DPTXFSIZ2	S3C_USBOTGREG(0x108)
+/* Device Periodic Transmit FIFO-3 Size */
+#define S3C_UDC_OTG_DPTXFSIZ3	S3C_USBOTGREG(0x10C)
+/* Device Periodic Transmit FIFO-4 Size */
+#define S3C_UDC_OTG_DPTXFSIZ4	S3C_USBOTGREG(0x110)
+/* Device Periodic Transmit FIFO-5 Size */
+#define S3C_UDC_OTG_DPTXFSIZ5	S3C_USBOTGREG(0x114)
+/* Device Periodic Transmit FIFO-6 Size */
+#define S3C_UDC_OTG_DPTXFSIZ6	S3C_USBOTGREG(0x118)
+/* Device Periodic Transmit FIFO-7 Size */
+#define S3C_UDC_OTG_DPTXFSIZ7	S3C_USBOTGREG(0x11C)
+/* Device Periodic Transmit FIFO-8 Size */
+#define S3C_UDC_OTG_DPTXFSIZ8	S3C_USBOTGREG(0x120)
+/* Device Periodic Transmit FIFO-9 Size */
+#define S3C_UDC_OTG_DPTXFSIZ9	S3C_USBOTGREG(0x124)
+/* Device Periodic Transmit FIFO-10 Size */
+#define S3C_UDC_OTG_DPTXFSIZ10	S3C_USBOTGREG(0x128)
+/* Device Periodic Transmit FIFO-11 Size */
+#define S3C_UDC_OTG_DPTXFSIZ11	S3C_USBOTGREG(0x12C)
+/* Device Periodic Transmit FIFO-12 Size */
+#define S3C_UDC_OTG_DPTXFSIZ12	S3C_USBOTGREG(0x130)
+/* Device Periodic Transmit FIFO-13 Size */
+#define S3C_UDC_OTG_DPTXFSIZ13	S3C_USBOTGREG(0x134)
+/* Device Periodic Transmit FIFO-14 Size */
+#define S3C_UDC_OTG_DPTXFSIZ14	S3C_USBOTGREG(0x138)
+/* Device Periodic Transmit FIFO-15 Size */
+#define S3C_UDC_OTG_DPTXFSIZ15	S3C_USBOTGREG(0x13C)
+
+/* Host Mode Registers
+ * Host Global Registers */
+/* Host Configuration */
+#define S3C_UDC_OTG_HCFG		S3C_USBOTGREG(0x400)
+/* Host Frame Interval */
+#define S3C_UDC_OTG_HFIR		S3C_USBOTGREG(0x404)
+/* Host Frame Number/Frame Time Remaining */
+#define S3C_UDC_OTG_HFNUM		S3C_USBOTGREG(0x408)
+/* Host Periodic Transmit FIFO/Queue Status */
+#define S3C_UDC_OTG_HPTXSTS		S3C_USBOTGREG(0x410)
+/* Host All Channels Interrupt */
+#define S3C_UDC_OTG_HAINT		S3C_USBOTGREG(0x414)
+/* Host All Channels Interrupt Mask */
+#define S3C_UDC_OTG_HAINTMSK	S3C_USBOTGREG(0x418)
+
+/* Host Port Control & Status Registers */
+#define S3C_UDC_OTG_HPRT		S3C_USBOTGREG(0x440)
+
+/* Host Channel-Specific Registers */
+/* Host Channel-0 Characteristics */
+#define  S3C_UDC_OTG_HCCHAR0	S3C_USBOTGREG(0x500)
+/* Host Channel-0 Split Control */
+#define  S3C_UDC_OTG_HCSPLT0	S3C_USBOTGREG(0x504)
+/* Host Channel-0 Interrupt */
+#define  S3C_UDC_OTG_HCINT0		S3C_USBOTGREG(0x508)
+/* Host Channel-0 Interrupt Mask */
+#define  S3C_UDC_OTG_HCINTMSK0	S3C_USBOTGREG(0x50C)
+/* Host Channel-0 Transfer Size */
+#define  S3C_UDC_OTG_HCTSIZ0	S3C_USBOTGREG(0x510)
+/* Host Channel-0 DMA Address */
+#define  S3C_UDC_OTG_HCDMA0		S3C_USBOTGREG(0x514)
+
+/* Device Mode Registers
+ * Device Global Registers */
+/* Device Configuration */
+#define  S3C_UDC_OTG_DCFG		S3C_USBOTGREG(0x800)
+/* Device Control */
+#define  S3C_UDC_OTG_DCTL		S3C_USBOTGREG(0x804)
+/* Device Status */
+#define  S3C_UDC_OTG_DSTS		S3C_USBOTGREG(0x808)
+/* Device IN Endpoint Common Interrupt Mask */
+#define  S3C_UDC_OTG_DIEPMSK	S3C_USBOTGREG(0x810)
+/* Device OUT Endpoint Common Interrupt Mask */
+#define  S3C_UDC_OTG_DOEPMSK	S3C_USBOTGREG(0x814)
+/* Device All Endpoints Interrupt */
+#define  S3C_UDC_OTG_DAINT		S3C_USBOTGREG(0x818)
+/* Device All Endpoints Interrupt Mask */
+#define  S3C_UDC_OTG_DAINTMSK	S3C_USBOTGREG(0x81C)
+/* Device IN Token Sequence Learning Queue Read 1 */
+#define  S3C_UDC_OTG_DTKNQR1	S3C_USBOTGREG(0x820)
+/* Device IN Token Sequence Learning Queue Read 2 */
+#define  S3C_UDC_OTG_DTKNQR2	S3C_USBOTGREG(0x824)
+/* Device VBUS Discharge Time */
+#define  S3C_UDC_OTG_DVBUSDIS	S3C_USBOTGREG(0x828)
+/* Device VBUS Pulsing Time */
+#define  S3C_UDC_OTG_DVBUSPULSE	S3C_USBOTGREG(0x82C)
+/* Device IN Token Sequence Learning Queue Read 3 */
+#define  S3C_UDC_OTG_DTKNQR3	S3C_USBOTGREG(0x830)
+/* Device IN Token Sequence Learning Queue Read 4 */
+#define  S3C_UDC_OTG_DTKNQR4	S3C_USBOTGREG(0x834)
+
+/* Device Logical IN Endpoint-Specific Registers */
+/* Device IN Endpoint 0 Control */
+#define  S3C_UDC_OTG_DIEPCTL0	S3C_USBOTGREG(0x900)
+/* Device IN Endpoint 0 Interrupt */
+#define  S3C_UDC_OTG_DIEPINT0	S3C_USBOTGREG(0x908)
+/* Device IN Endpoint 0 Transfer Size */
+#define  S3C_UDC_OTG_DIEPTSIZ0	S3C_USBOTGREG(0x910)
+/* Device IN Endpoint 0 DMA Address */
+#define  S3C_UDC_OTG_DIEPDMA0	S3C_USBOTGREG(0x914)
+
+/* Device IN Endpoint 2 Control */
+#define  S3C_UDC_OTG_DIEPCTL2	S3C_USBOTGREG(0x940)
+/* Device IN Endpoint 2 Interrupt */
+#define  S3C_UDC_OTG_DIEPINT2	S3C_USBOTGREG(0x948)
+/* Device IN Endpoint 2 Transfer Size */
+#define  S3C_UDC_OTG_DIEPTSIZ2	S3C_USBOTGREG(0x950)
+/* Device IN Endpoint 2 DMA Address */
+#define  S3C_UDC_OTG_DIEPDMA2	S3C_USBOTGREG(0x954)
+
+/* Device IN Endpoint 3 Control */
+#define  S3C_UDC_OTG_DIEPCTL3	S3C_USBOTGREG(0x960)
+/* Device IN Endpoint 3 Interrupt */
+#define  S3C_UDC_OTG_DIEPINT3	S3C_USBOTGREG(0x968)
+/* Device IN Endpoint 3 Transfer Size */
+#define  S3C_UDC_OTG_DIEPTSIZ3	S3C_USBOTGREG(0x970)
+/* Device IN Endpoint 3 DMA Address */
+#define  S3C_UDC_OTG_DIEPDMA3	S3C_USBOTGREG(0x974)
+
+/* Device Logical OUT Endpoint-Specific Registers */
+/* Device OUT Endpoint 0 Control */
+#define  S3C_UDC_OTG_DOEPCTL0	S3C_USBOTGREG(0xB00)
+/* Device OUT Endpoint 0 Interrupt */
+#define  S3C_UDC_OTG_DOEPINT0	S3C_USBOTGREG(0xB08)
+/* Device OUT Endpoint 0 Transfer Size */
+#define  S3C_UDC_OTG_DOEPTSIZ0	S3C_USBOTGREG(0xB10)
+/* Device OUT Endpoint 0 DMA Address */
+#define  S3C_UDC_OTG_DOEPDMA0	S3C_USBOTGREG(0xB14)
+
+/* Device OUT Endpoint 1 Control */
+#define  S3C_UDC_OTG_DOEPCTL1	S3C_USBOTGREG(0xB20)
+/* Device OUT Endpoint 1 Interrupt */
+#define  S3C_UDC_OTG_DOEPINT1	S3C_USBOTGREG(0xB28)
+/* Device OUT Endpoint 1 Transfer Size */
+#define  S3C_UDC_OTG_DOEPTSIZ1	S3C_USBOTGREG(0xB30)
+/* Device OUT Endpoint 1 DMA Address */
+#define  S3C_UDC_OTG_DOEPDMA1	S3C_USBOTGREG(0xB34)
+
+/* Endpoint FIFO address */
+#define S3C_UDC_OTG_EP0_FIFO	S3C_USBOTGREG(0x1000)
+#define S3C_UDC_OTG_EP1_FIFO	S3C_USBOTGREG(0x2000)
+#define S3C_UDC_OTG_EP2_FIFO	S3C_USBOTGREG(0x3000)
+#define S3C_UDC_OTG_EP3_FIFO	S3C_USBOTGREG(0x4000)
+#define S3C_UDC_OTG_EP4_FIFO	S3C_USBOTGREG(0x5000)
+#define S3C_UDC_OTG_EP5_FIFO	S3C_USBOTGREG(0x6000)
+#define S3C_UDC_OTG_EP6_FIFO	S3C_USBOTGREG(0x7000)
+#define S3C_UDC_OTG_EP7_FIFO	S3C_USBOTGREG(0x8000)
+#define S3C_UDC_OTG_EP8_FIFO	S3C_USBOTGREG(0x9000)
+
+/* S3C_USBOTG_PHYPWR */
+#define OTG_ENABLE			(0x0<<4)
+#define OTG_DISABLE			(0x1<<4)
+#define ANALOG_PWR_UP		(0x0<<3)
+#define ANALOG_PWR_DOWN		(0x1<<3)
+#define SUSPEND_DISABLE		(0x0<<0)
+#define SUSPEND_ENABLE		(0x1<<0)
+
+/* S3C_USBOTG_PHYCLK */
+#define REF_CLK_CRYSTAL		(0x0<<5)
+#define REF_CLK_OSCC		(0x1<<5)
+
+/* S3C_USBOTG_RSTCON */
+#define SW_RST_OFF			(0x0<<0)
+#define SW_RST_ON			(0x1<<0)
+
+/* S3C_UDC_OTG_GOTGCTL */
+#define B_SESSION_VALID		(0x1<<19)
+#define A_SESSION_VALID		(0x1<<18)
+
+/* S3C_UDC_OTG_GAHBCFG */
+#define PTXFE_HALF			(0x0<<8)
+#define PTXFE_ZERO			(0x1<<8)
+#define NPTXFE_HALF			(0x0<<7)
+#define NPTXFE_ZERO			(0x1<<7)
+#define MODE_SLAVE			(0x0<<5)
+#define MODE_DMA			(0x1<<5)
+#define BURST_SINGLE		(0x0<<1)
+#define BURST_INCR			(0x1<<1)
+#define BURST_INCR4			(0x3<<1)
+#define BURST_INCR8			(0x5<<1)
+#define BURST_INCR16		(0x7<<1)
+#define GBL_INT_UNMASK		(0x1<<0)
+#define GBL_INT_MASK		(0x0<<0)
+
+/* S3C_UDC_OTG_GUSBCFG */
+#define PHY_CLK_480M		(0x0<<15)
+#define PHY_CLK_48M			(0x1<<15)
+#define TXFIFO_RE_DIS		(0x0<<14)
+#define TXFIFO_RE_EN		(0x1<<14)
+#define TURN_AROUND			(0x5<<10)
+#define HNP_DISABLE			(0x0<<9)
+#define HNP_ENABLE			(0x1<<9)
+#define SRP_DISABLE			(0x0<<8)
+#define SRP_ENABLE			(0x1<<8)
+#define ULPI_DDR			(0x0<<7)
+#define HS_UTMI				(0x0<<6)
+#define INTERF_UTMI			(0x0<<4)
+#define INTERF_ULPI			(0x1<<4)
+#define PHY_INTERF_8		(0x0<<3)
+#define PHY_INTERF_16		(0x1<<3)
+#define TIME_OUT_CAL		(0x7<<0)
+
+/* S3C_UDC_OTG_GRSTCTL */
+#define AHB_MASTER_IDLE		(1u<<31)
+#define CORE_SOFT_RESET		(0x1<<0)
+
+/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
+#define INT_RESUME			(0x1<<31)
+#define INT_DISCONN			(0x1<<29)
+#define INT_CONN_CNG		(0x1<<28)
+#define INT_OUT_EP			(0x1<<19)
+#define INT_IN_EP			(0x1<<18)
+#define INT_ENUMDONE		(0x1<<13)
+#define INT_RESET			(0x1<<12)
+#define INT_SUSPEND			(0x1<<11)
+#define INT_EARLY_SUSPEND	(0x1<<10)
+#define INT_TX_FIFO_EMPTY	(0x1<<5)
+#define INT_RX_FIFO_NOT_EMPTY	(0x1<<4)
+#define INT_SOF				(0x1<<3)
+#define INT_DEV_MODE		(0x0<<0)
+#define INT_HOST_MODE		(0x1<<1)
+
+#define FULL_SPEED_CONTROL_PKT_SIZE		8
+#define FULL_SPEED_BULK_PKT_SIZE		64
+
+#define HIGH_SPEED_CONTROL_PKT_SIZE		64
+#define HIGH_SPEED_BULK_PKT_SIZE		512
+
+/* S3C_UDC_OTG_DSTS */
+#define RX_FIFO_SIZE		(2048<<0)
+#define NPTX_FIFO_START_ADDR	(RX_FIFO_SIZE<<0)
+#define NPTX_FIFO_SIZE		(2048<<16)
+#define PTX_FIFO_SIZE		(2048<<16)
+#define USB_HIGH_30_60MHZ	(0x0<<1)
+#define USB_FULL_30_60MHZ	(0x1<<1)
+#define USB_LOW_6MHZ		(0x2<<1)
+#define USB_FULL_48MHZ		(0x3<<1)
+
+/* S3C_UDC_OTG_GRXSTSP */
+#define BYTE_COUNT(x)		((x & (0x7FF<<4)) >> 4)
+#define PKT_STS(x)			((x & (0xF<<17)) >> 17)
+#define EP_NUM(x)			(x & 0xF)
+
+#define OUT_PKT_RECEIVED	(0x2)
+#define OUT_COMPLELTED		(0x3)
+#define SETUP_COMPLETED		(0x4)
+#define SETUP_PKT_RECEIVED	(0x6)
+
+/* S3C_UDC_OTG_DCFG */
+#define EP_MIS_CNT(x)		(x<<18)
+#define DEVICE_ADDR(x)		(x<<4)
+#define SPEED_2_HIGH		(0x0<<0)
+#define SPEED_2_FULL		(0x1<<0)
+#define SPEED_1_LOW			(0x2<<0)
+#define SPEED_1_FULL		(0x3<<0)
+
+/* S3C_UDC_OTG_DCTL device control register */
+#define NORMAL_OPERATION	(0x1<<0)
+#define SOFT_DISCONNECT		(0x1<<1)
+
+/* S3C_UDC_OTG_DSTS */
+#define ENUM_SPEED(x)		(x & (0x3<<1))
+#define FRAME_CNT(x)		(x & (0x3ff<<8))
+
+/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
+#define S3C_UDC_INT_IN_EP0	(0x1<<0)
+#define S3C_UDC_INT_IN_EP2	(0x1<<2)
+#define S3C_UDC_INT_IN_EP3	(0x1<<3)
+#define S3C_UDC_INT_OUT_EP0	(0x1<<16)
+#define S3C_UDC_INT_OUT_EP1	(0x1<<17)
+#define S3C_UDC_INT_OUT_EP4	(0x1<<20)
+
+/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control
+   IN/OUT endpoint 0 control register */
+#define DEPCTL_EPENA		(0x1<<31)
+#define DEPCTL_EPDIS		(0x1<<30)
+#define DEPCTL_SNAK			(0x1<<27)
+#define DEPCTL_CNAK			(0x1<<26)
+#define DEPCTL_CTRL_TYPE	(0x0<<18)
+#define DEPCTL_ISO_TYPE		(0x1<<18)
+#define DEPCTL_BULK_TYPE	(0x2<<18)
+#define DEPCTL_INTR_TYPE	(0x3<<18)
+#define DEPCTL_USBACTEP		(0x1<<15)
+#define DEPCTL0_MPS_64		(0x0<<0)
+#define DEPCTL0_MPS_32		(0x1<<0)
+#define DEPCTL0_MPS_16		(0x2<<0)
+#define DEPCTL0_MPS_8		(0x3<<0)
+
+/* S3C_UDC_OTG_DIEPINTn */
+#define IN_EP_NAK_EFF		(0x1<<6)
+#define IN_TK_EPMIS			(0x1<<5)
+#define IN_TK_TXFEMP		(0x1<<4)
+#define IN_EP_TIMEOUT		(0x1<<3)
+
+/* S3C_UDC_OTG_DOEPINTn */
+#define BACK2BACK_SETUP		(0x1<<6)
+#define OUT_TK_EP_DIS		(0x1<<4)
+#define SETUP_PHASE_DONE	(0x1<<3)
+
+/* S3C_UDC_OTG_DIEPINTn/DOEPINTn */
+#define AHB_ERROR			(0x1<<2)
+#define EPDISBLD			(0x1<<1)
+#define TRANSFER_DONE		(0x1<<0)
+
+/* S3C_UDC_OTG_DIEPTSIZn */
+#define PKT_CNT(x)			(x<<19)
+#define XFERSIZE(x)			(x<<0)
+
+#endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/sdhci.h android_2.6.29/arch/arm/plat-s3c/include/plat/sdhci.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/sdhci.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/sdhci.h	2009-04-10 11:13:25.000000000 +0900
@@ -29,6 +29,7 @@
  *            is necessary the controllers and/or GPIO blocks require the
  *	      changing of driver-strength and other controls dependant on
  *	      the card and speed of operation.
+ * sdhci_host: Pointer kept during init, allows presence change notification
  *
  * Initialisation data specific to either the machine or the platform
  * for the device driver to use or call-back when configuring gpio or
@@ -45,8 +46,11 @@
 			    void __iomem *regbase,
 			    struct mmc_ios *ios,
 			    struct mmc_card *card);
+	struct sdhci_host * sdhci_host;
 };
 
+extern void sdhci_s3c_force_presence_change(struct platform_device *pdev);
+
 /**
  * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
  * @pd: Platform data to register to device.
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/ts.h android_2.6.29/arch/arm/plat-s3c/include/plat/ts.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/ts.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/ts.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,42 @@
+/* arch/arm/plat-s3c/include/plat/ts.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TS_H
+#define __ASM_ARCH_TS_H __FILE__
+
+
+enum s3c_adc_type {
+	ADC_TYPE_0,
+	ADC_TYPE_1,	/* S3C2416, S3C2450 */
+	ADC_TYPE_2,	/* S3C64XX, S5PC1XX */
+};
+
+struct s3c_ts_mach_info {
+	int             	delay;
+	int             	presc;
+	int             	oversampling_shift;
+	int			resol_bit;
+	enum s3c_adc_type	s3c_adc_con;
+};
+
+struct s3c_ts_info {
+	struct input_dev 	*dev;
+	long 			xp;
+	long 			yp;
+	int 			count;
+	int 			shift;
+	char 			phys[32];
+	int			resol_bit;
+	enum s3c_adc_type	s3c_adc_con;
+};
+
+extern void __init s3c_ts_set_platdata(struct s3c_ts_mach_info *pd);
+
+#endif /* __ASM_ARCH_TS_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/include/plat/usb-control.h android_2.6.29/arch/arm/plat-s3c/include/plat/usb-control.h
--- android_2.6.29_org/arch/arm/plat-s3c/include/plat/usb-control.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/include/plat/usb-control.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,41 @@
+/* arch/arm/plat-s3c/include/plat/usb-control.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - usb port information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_USBCONTROL_H
+#define __ASM_ARCH_USBCONTROL_H "arch/arm/plat-s3c/include/plat/usb-control.h"
+
+#define S3C_HCDFLG_USED	(1)
+
+struct s3c2410_hcd_port {
+	unsigned char	flags;
+	unsigned char	power;
+	unsigned char	oc_status;
+	unsigned char	oc_changed;
+};
+
+struct s3c2410_hcd_info {
+	struct usb_hcd		*hcd;
+	struct s3c2410_hcd_port	port[2];
+
+	void		(*power_control)(int port, int to);
+	void		(*enable_oc)(struct s3c2410_hcd_info *, int on);
+	void		(*report_oc)(struct s3c2410_hcd_info *, int ports);
+};
+
+static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
+{
+	if (info->report_oc != NULL) {
+		(info->report_oc)(info, ports);
+	}
+}
+
+#endif /*__ASM_ARCH_USBCONTROL_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c/init.c android_2.6.29/arch/arm/plat-s3c/init.c
--- android_2.6.29_org/arch/arm/plat-s3c/init.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/init.c	2009-04-10 11:13:25.000000000 +0900
@@ -31,6 +31,33 @@
 
 static struct cpu_table *cpu;
 
+static void __init set_system_rev(unsigned int idcode)
+{
+	/*
+	 * system_rev encoding is as follows
+	 * system_rev & 0xff000000 -> S3C Class (24xx/64xx)
+	 * system_rev & 0xfff00000 -> S3C Sub Class (241x/244x)
+	 * system_rev & 0xffff0000 -> S3C Type (2410/2440/6400/6410)
+	 *
+	 * Remaining[15:0] are preserved from the value set by ATAG
+	 *
+	 * Exception:
+	 *  Store Revision A to 1 such as
+	 *  s3c2410A to s3c2411
+	 *  s3c2440A to s3c2441
+	 */
+
+	system_rev &= 0xffff;
+	system_rev |= (idcode & 0x0ffff000) << 4;
+
+	if (idcode == 0x32410002 || idcode == 0x32440001)
+		system_rev |= (0x1 << 16);
+	if (idcode == 0x32440aaa)	/* s3c2442 */
+		system_rev |= (0x2 << 16);
+	if (idcode == 0x0)		/* s3c2400 */
+		system_rev |= (0x2400 << 16);
+}
+
 static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
 						struct cpu_table *tab,
 						unsigned int count)
@@ -53,6 +80,8 @@
 		panic("Unknown S3C24XX CPU");
 	}
 
+	set_system_rev(idcode);
+
 	printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
 
 	if (cpu->map_io == NULL || cpu->init == NULL) {
diff -urN android_2.6.29_org/arch/arm/plat-s3c/pm-check.c android_2.6.29/arch/arm/plat-s3c/pm-check.c
--- android_2.6.29_org/arch/arm/plat-s3c/pm-check.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/pm-check.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,242 @@
+/* linux/arch/arm/plat-s3c/pm-check.c
+ *  originally in linux/arch/arm/plat-s3c24xx/pm.c
+ *
+ * Copyright (c) 2004,2006,2008 Simtec Electronics
+ *	http://armlinux.simtec.co.uk
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Power Mangament - suspend/resume memory corruptiuon check.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/init.h>
+#include <linux/crc32.h>
+#include <linux/ioport.h>
+
+#include <plat/pm.h>
+
+#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1
+#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value
+#endif
+
+/* suspend checking code...
+ *
+ * this next area does a set of crc checks over all the installed
+ * memory, so the system can verify if the resume was ok.
+ *
+ * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
+ * increasing it will mean that the area corrupted will be less easy to spot,
+ * and reducing the size will cause the CRC save area to grow
+*/
+
+#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
+
+static u32 crc_size;	/* size needed for the crc block */
+static u32 *crcs;	/* allocated over suspend/resume */
+
+typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
+
+/* s3c_pm_run_res
+ *
+ * go through the given resource list, and look for system ram
+*/
+
+static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
+{
+	while (ptr != NULL) {
+		if (ptr->child != NULL)
+			s3c_pm_run_res(ptr->child, fn, arg);
+
+		if ((ptr->flags & IORESOURCE_MEM) &&
+		    strcmp(ptr->name, "System RAM") == 0) {
+			S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
+				  (unsigned long)ptr->start,
+				  (unsigned long)ptr->end);
+			arg = (fn)(ptr, arg);
+		}
+
+		ptr = ptr->sibling;
+	}
+}
+
+static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
+{
+	s3c_pm_run_res(&iomem_resource, fn, arg);
+}
+
+static u32 *s3c_pm_countram(struct resource *res, u32 *val)
+{
+	u32 size = (u32)(res->end - res->start)+1;
+
+	size += CHECK_CHUNKSIZE-1;
+	size /= CHECK_CHUNKSIZE;
+
+	S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
+		  (unsigned long)res->start, (unsigned long)res->end, size);
+
+	*val += size * sizeof(u32);
+	return val;
+}
+
+/* s3c_pm_prepare_check
+ *
+ * prepare the necessary information for creating the CRCs. This
+ * must be done before the final save, as it will require memory
+ * allocating, and thus touching bits of the kernel we do not
+ * know about.
+*/
+
+void s3c_pm_check_prepare(void)
+{
+	crc_size = 0;
+
+	s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
+
+	S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
+
+	crcs = kmalloc(crc_size+4, GFP_KERNEL);
+	if (crcs == NULL)
+		printk(KERN_ERR "Cannot allocated CRC save area\n");
+}
+
+static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
+{
+	unsigned long addr, left;
+
+	for (addr = res->start; addr < res->end;
+	     addr += CHECK_CHUNKSIZE) {
+		left = res->end - addr;
+
+		if (left > CHECK_CHUNKSIZE)
+			left = CHECK_CHUNKSIZE;
+
+		*val = crc32_le(~0, phys_to_virt(addr), left);
+		val++;
+	}
+
+	return val;
+}
+
+/* s3c_pm_check_store
+ *
+ * compute the CRC values for the memory blocks before the final
+ * sleep.
+*/
+
+void s3c_pm_check_store(void)
+{
+	if (crcs != NULL)
+		s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
+}
+
+/* in_region
+ *
+ * return TRUE if the area defined by ptr..ptr+size contains the
+ * what..what+whatsz
+*/
+
+static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
+{
+	if ((what+whatsz) < ptr)
+		return 0;
+
+	if (what > (ptr+size))
+		return 0;
+
+	return 1;
+}
+
+/**
+ * s3c_pm_runcheck() - helper to check a resource on restore.
+ * @res: The resource to check
+ * @vak: Pointer to list of CRC32 values to check.
+ *
+ * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
+ * function runs the given memory resource checking it against the stored
+ * CRC to ensure that memory is restored. The function tries to skip as
+ * many of the areas used during the suspend process.
+ */
+static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
+{
+	void *save_at = phys_to_virt(s3c_sleep_save_phys);
+	unsigned long addr;
+	unsigned long left;
+	void *stkpage;
+	void *ptr;
+	u32 calc;
+
+	stkpage = (void *)((u32)&calc & ~PAGE_MASK);
+
+	for (addr = res->start; addr < res->end;
+	     addr += CHECK_CHUNKSIZE) {
+		left = res->end - addr;
+
+		if (left > CHECK_CHUNKSIZE)
+			left = CHECK_CHUNKSIZE;
+
+		ptr = phys_to_virt(addr);
+
+		if (in_region(ptr, left, stkpage, 4096)) {
+			S3C_PMDBG("skipping %08lx, has stack in\n", addr);
+			goto skip_check;
+		}
+
+		if (in_region(ptr, left, crcs, crc_size)) {
+			S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
+			goto skip_check;
+		}
+
+		if (in_region(ptr, left, save_at, 32*4 )) {
+			S3C_PMDBG("skipping %08lx, has save block in\n", addr);
+			goto skip_check;
+		}
+
+		/* calculate and check the checksum */
+
+		calc = crc32_le(~0, ptr, left);
+		if (calc != *val) {
+			printk(KERN_ERR "Restore CRC error at "
+			       "%08lx (%08x vs %08x)\n", addr, calc, *val);
+
+			S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
+			    addr, calc, *val);
+		}
+
+	skip_check:
+		val++;
+	}
+
+	return val;
+}
+
+/**
+ * s3c_pm_check_restore() - memory check called on resume
+ *
+ * check the CRCs after the restore event and free the memory used
+ * to hold them
+*/
+void s3c_pm_check_restore(void)
+{
+	if (crcs != NULL)
+		s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
+}
+
+/**
+ * s3c_pm_check_cleanup() - free memory resources
+ *
+ * Free the resources that where allocated by the suspend
+ * memory check code. We do this separately from the
+ * s3c_pm_check_restore() function as we cannot call any
+ * functions that might sleep during that resume.
+ */
+void s3c_pm_check_cleanup(void)
+{
+	kfree(crcs);
+	crcs = NULL;
+}
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c/pm-gpio.c android_2.6.29/arch/arm/plat-s3c/pm-gpio.c
--- android_2.6.29_org/arch/arm/plat-s3c/pm-gpio.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/pm-gpio.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,378 @@
+/* linux/arch/arm/plat-s3c/pm-gpio.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/gpio-core.h>
+#include <plat/pm.h>
+
+/* PM GPIO helpers */
+
+#define OFFS_CON	(0x00)
+#define OFFS_DAT	(0X04)
+#define OFFS_UP		(0X08)
+
+static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
+{
+	chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+	chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+}
+
+static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
+{
+	void __iomem *base = chip->base;
+	u32 old_gpcon = __raw_readl(base + OFFS_CON);
+	u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+	u32 gps_gpcon = chip->pm_save[0];
+	u32 gps_gpdat = chip->pm_save[1];
+	u32 gpcon;
+
+	/* GPACON only has one bit per control / data and no PULLUPs.
+	 * GPACON[x] = 0 => Output, 1 => SFN */
+
+	/* first set all SFN bits to SFN */
+
+	gpcon = old_gpcon | gps_gpcon;
+	__raw_writel(gpcon, base + OFFS_CON);
+
+	/* now set all the other bits */
+
+	__raw_writel(gps_gpdat, base + OFFS_DAT);
+	__raw_writel(gps_gpcon, base + OFFS_CON);
+
+	S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+		  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_1bit = {
+	.save	= s3c_gpio_pm_1bit_save,
+	.resume = s3c_gpio_pm_1bit_resume,
+};
+
+static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
+{
+	chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+	chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+	chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+}
+
+/* Test whether the given masked+shifted bits of an GPIO configuration
+ * are one of the SFN (special function) modes. */
+
+static inline int is_sfn(unsigned long con)
+{
+	return con >= 2;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an input */
+
+static inline int is_in(unsigned long con)
+{
+	return con == 0;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an output */
+
+static inline int is_out(unsigned long con)
+{
+	return con == 1;
+}
+
+/**
+ * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
+ * @chip: The chip information to resume.
+ *
+ * Restore one of the GPIO banks that was saved during suspend. This is
+ * not as simple as once thought, due to the possibility of glitches
+ * from the order that the CON and DAT registers are set in.
+ *
+ * The three states the pin can be are {IN,OUT,SFN} which gives us 9
+ * combinations of changes to check. Three of these, if the pin stays
+ * in the same configuration can be discounted. This leaves us with
+ * the following:
+ *
+ * { IN => OUT }  Change DAT first
+ * { IN => SFN }  Change CON first
+ * { OUT => SFN } Change CON first, so new data will not glitch
+ * { OUT => IN }  Change CON first, so new data will not glitch
+ * { SFN => IN }  Change CON first
+ * { SFN => OUT } Change DAT first, so new data will not glitch [1]
+ *
+ * We do not currently deal with the UP registers as these control
+ * weak resistors, so a small delay in change should not need to bring
+ * these into the calculations.
+ *
+ * [1] this assumes that writing to a pin DAT whilst in SFN will set the
+ *     state for when it is next output.
+ */
+static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
+{
+	void __iomem *base = chip->base;
+	u32 old_gpcon = __raw_readl(base + OFFS_CON);
+	u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+	u32 gps_gpcon = chip->pm_save[0];
+	u32 gps_gpdat = chip->pm_save[1];
+	u32 gpcon, old, new, mask;
+	u32 change_mask = 0x0;
+	int nr;
+
+	/* restore GPIO pull-up settings */
+	__raw_writel(chip->pm_save[2], base + OFFS_UP);
+
+	/* Create a change_mask of all the items that need to have
+	 * their CON value changed before their DAT value, so that
+	 * we minimise the work between the two settings.
+	 */
+
+	for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
+		old = (old_gpcon & mask) >> nr;
+		new = (gps_gpcon & mask) >> nr;
+
+		/* If there is no change, then skip */
+
+		if (old == new)
+			continue;
+
+		/* If both are special function, then skip */
+
+		if (is_sfn(old) && is_sfn(new))
+			continue;
+
+		/* Change is IN => OUT, do not change now */
+
+		if (is_in(old) && is_out(new))
+			continue;
+
+		/* Change is SFN => OUT, do not change now */
+
+		if (is_sfn(old) && is_out(new))
+			continue;
+
+		/* We should now be at the case of IN=>SFN,
+		 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+		change_mask |= mask;
+	}
+
+
+	/* Write the new CON settings */
+
+	gpcon = old_gpcon & ~change_mask;
+	gpcon |= gps_gpcon & change_mask;
+
+	__raw_writel(gpcon, base + OFFS_CON);
+
+	/* Now change any items that require DAT,CON */
+
+	__raw_writel(gps_gpdat, base + OFFS_DAT);
+	__raw_writel(gps_gpcon, base + OFFS_CON);
+
+	S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+		  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_2bit = {
+	.save	= s3c_gpio_pm_2bit_save,
+	.resume = s3c_gpio_pm_2bit_resume,
+};
+
+#ifdef CONFIG_ARCH_S3C64XX
+static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
+{
+	chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
+	chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
+	chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+
+	if (chip->chip.ngpio > 8)
+		chip->pm_save[0] = __raw_readl(chip->base - 4);
+}
+
+static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
+{
+	u32 old, new, mask;
+	u32 change_mask = 0x0;
+	int nr;
+
+	for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
+		old = (old_gpcon & mask) >> nr;
+		new = (gps_gpcon & mask) >> nr;
+
+		/* If there is no change, then skip */
+
+		if (old == new)
+			continue;
+
+		/* If both are special function, then skip */
+
+		if (is_sfn(old) && is_sfn(new))
+			continue;
+
+		/* Change is IN => OUT, do not change now */
+
+		if (is_in(old) && is_out(new))
+			continue;
+
+		/* Change is SFN => OUT, do not change now */
+
+		if (is_sfn(old) && is_out(new))
+			continue;
+
+		/* We should now be at the case of IN=>SFN,
+		 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+		change_mask |= mask;
+	}
+
+	return change_mask;
+}
+
+static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
+{
+	void __iomem *con = chip->base + (index * 4);
+	u32 old_gpcon = __raw_readl(con);
+	u32 gps_gpcon = chip->pm_save[index + 1];
+	u32 gpcon, mask;
+
+	mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
+
+	gpcon = old_gpcon & ~mask;
+	gpcon |= gps_gpcon & mask;
+
+	__raw_writel(gpcon, con);
+}
+
+static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
+{
+	void __iomem *base = chip->base;
+	u32 old_gpcon[2];
+	u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+	u32 gps_gpdat = chip->pm_save[2];
+
+	/* First, modify the CON settings */
+
+	old_gpcon[0] = 0;
+	old_gpcon[1] = __raw_readl(base + OFFS_CON);
+
+	s3c_gpio_pm_4bit_con(chip, 0);
+	if (chip->chip.ngpio > 8) {
+		old_gpcon[0] = __raw_readl(base - 4);
+		s3c_gpio_pm_4bit_con(chip, -1);
+	}
+
+	/* Now change the configurations that require DAT,CON */
+
+	__raw_writel(chip->pm_save[2], base + OFFS_DAT);
+	__raw_writel(chip->pm_save[1], base + OFFS_CON);
+	if (chip->chip.ngpio > 8)
+		__raw_writel(chip->pm_save[0], base - 4);
+
+	__raw_writel(chip->pm_save[2], base + OFFS_DAT);
+	__raw_writel(chip->pm_save[3], base + OFFS_UP);
+
+	if (chip->chip.ngpio > 8) {
+		S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
+			  chip->chip.label, old_gpcon[0], old_gpcon[1],
+			  __raw_readl(base - 4),
+			  __raw_readl(base + OFFS_CON),
+			  old_gpdat, gps_gpdat);
+	} else
+		S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
+			  chip->chip.label, old_gpcon[1],
+			  __raw_readl(base + OFFS_CON),
+			  old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_4bit = {
+	.save	= s3c_gpio_pm_4bit_save,
+	.resume = s3c_gpio_pm_4bit_resume,
+};
+#endif /* CONFIG_ARCH_S3C64XX */
+
+/**
+ * s3c_pm_save_gpio() - save gpio chip data for suspend
+ * @ourchip: The chip for suspend.
+ */
+static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
+{
+	struct s3c_gpio_pm *pm = ourchip->pm;
+
+	if (pm == NULL || pm->save == NULL)
+		S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+	else
+		pm->save(ourchip);
+}
+
+/**
+ * s3c_pm_save_gpios() - Save the state of the GPIO banks.
+ *
+ * For all the GPIO banks, save the state of each one ready for going
+ * into a suspend mode.
+ */
+void s3c_pm_save_gpios(void)
+{
+	struct s3c_gpio_chip *ourchip;
+	unsigned int gpio_nr;
+
+	for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+		ourchip = s3c_gpiolib_getchip(gpio_nr);
+		if (!ourchip)
+			continue;
+
+		s3c_pm_save_gpio(ourchip);
+
+		S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
+			  ourchip->chip.label,
+			  ourchip->pm_save[0],
+			  ourchip->pm_save[1],
+			  ourchip->pm_save[2],
+			  ourchip->pm_save[3]);
+
+		gpio_nr += ourchip->chip.ngpio;
+		gpio_nr += CONFIG_S3C_GPIO_SPACE;
+	}
+}
+
+/**
+ * s3c_pm_resume_gpio() - restore gpio chip data after suspend
+ * @ourchip: The suspended chip.
+ */
+static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
+{
+	struct s3c_gpio_pm *pm = ourchip->pm;
+
+	if (pm == NULL || pm->resume == NULL)
+		S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+	else
+		pm->resume(ourchip);
+}
+
+void s3c_pm_restore_gpios(void)
+{
+	struct s3c_gpio_chip *ourchip;
+	unsigned int gpio_nr;
+
+	for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+		ourchip = s3c_gpiolib_getchip(gpio_nr);
+		if (!ourchip)
+			continue;
+
+		s3c_pm_resume_gpio(ourchip);
+
+		gpio_nr += ourchip->chip.ngpio;
+		gpio_nr += CONFIG_S3C_GPIO_SPACE;
+	}
+}
diff -urN android_2.6.29_org/arch/arm/plat-s3c/pm.c android_2.6.29/arch/arm/plat-s3c/pm.c
--- android_2.6.29_org/arch/arm/plat-s3c/pm.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/pm.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,375 @@
+/* linux/arch/arm/plat-s3c/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2004,2006,2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C common power management (suspend to ram) support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-irq.h>
+#include <asm/irq.h>
+
+#include <plat/pm.h>
+#include <plat/pm-core.h>
+
+/* for external use */
+
+unsigned long s3c_pm_flags;
+
+/* Debug code:
+ *
+ * This code supports debug output to the low level UARTs for use on
+ * resume before the console layer is available.
+*/
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+extern void printascii(const char *);
+
+void s3c_pm_dbg(const char *fmt, ...)
+{
+	va_list va;
+	char buff[256];
+
+	va_start(va, fmt);
+	vsprintf(buff, fmt, va);
+	va_end(va);
+
+	printascii(buff);
+}
+
+static inline void s3c_pm_debug_init(void)
+{
+	/* restart uart clocks so we can use them to output */
+	s3c_pm_debug_init_uart();
+}
+
+#else
+#define s3c_pm_debug_init() do { } while(0)
+
+#endif /* CONFIG_S3C2410_PM_DEBUG */
+
+/* Save the UART configurations if we are configured for debug. */
+
+unsigned char pm_uart_udivslot;
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+
+struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
+{
+	void __iomem *regs = S3C_VA_UARTx(uart);
+
+	save->ulcon = __raw_readl(regs + S3C2410_ULCON);
+	save->ucon = __raw_readl(regs + S3C2410_UCON);
+	save->ufcon = __raw_readl(regs + S3C2410_UFCON);
+	save->umcon = __raw_readl(regs + S3C2410_UMCON);
+	save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+
+	if (pm_uart_udivslot)
+		save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+
+	S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
+		  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
+}
+
+static void s3c_pm_save_uarts(void)
+{
+	struct pm_uart_save *save = uart_save;
+	unsigned int uart;
+
+	for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+		s3c_pm_save_uart(uart, save);
+}
+
+static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
+{
+	void __iomem *regs = S3C_VA_UARTx(uart);
+
+	s3c_pm_arch_update_uart(regs, save);
+
+	__raw_writel(save->ulcon, regs + S3C2410_ULCON);
+	__raw_writel(save->ucon,  regs + S3C2410_UCON);
+	__raw_writel(save->ufcon, regs + S3C2410_UFCON);
+	__raw_writel(save->umcon, regs + S3C2410_UMCON);
+	__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+
+	if (pm_uart_udivslot)
+		__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+}
+
+static void s3c_pm_restore_uarts(void)
+{
+	struct pm_uart_save *save = uart_save;
+	unsigned int uart;
+
+	for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+		s3c_pm_restore_uart(uart, save);
+}
+#else
+static void s3c_pm_save_uarts(void) { }
+static void s3c_pm_restore_uarts(void) { }
+#endif
+
+/* The IRQ ext-int code goes here, it is too small to currently bother
+ * with its own file. */
+
+unsigned long s3c_irqwake_intmask	= 0xffffffffL;
+unsigned long s3c_irqwake_eintmask	= 0xffffffffL;
+
+int s3c_irqext_wake(unsigned int irqno, unsigned int state)
+{
+	unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
+
+	if (!(s3c_irqwake_eintallow & bit))
+		return -ENOENT;
+
+	printk(KERN_INFO "wake %s for irq %d\n",
+	       state ? "enabled" : "disabled", irqno);
+
+	if (!state)
+		s3c_irqwake_eintmask |= bit;
+	else
+		s3c_irqwake_eintmask &= ~bit;
+
+	return 0;
+}
+
+/* helper functions to save and restore register state */
+
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+	for (; count > 0; count--, ptr++) {
+		ptr->val = __raw_readl(ptr->reg);
+		S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+	}
+}
+
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * Note, we do not use S3C_PMDBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
+
+void s3c_pm_do_restore(struct sleep_save *ptr, int count)
+{
+	for (; count > 0; count--, ptr++) {
+		printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
+		       ptr->reg, ptr->val, __raw_readl(ptr->reg));
+
+		__raw_writel(ptr->val, ptr->reg);
+	}
+}
+
+/**
+ * s3c_pm_do_restore_core() - early restore register values from save list.
+ *
+ * This is similar to s3c_pm_do_restore() except we try and minimise the
+ * side effects of the function in case registers that hardware might need
+ * to work has been restored.
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+
+void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
+{
+	for (; count > 0; count--, ptr++)
+		__raw_writel(ptr->val, ptr->reg);
+}
+
+/* s3c2410_pm_show_resume_irqs
+ *
+ * print any IRQs asserted at resume time (ie, we woke from)
+*/
+static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+				    unsigned long mask)
+{
+	int i;
+
+	which &= ~mask;
+
+	for (i = 0; i <= 31; i++) {
+		if (which & (1L<<i)) {
+			S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
+		}
+	}
+}
+
+
+void (*pm_cpu_prep)(void);
+void (*pm_cpu_sleep)(void);
+
+#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
+
+/* s3c_pm_enter
+ *
+ * central control for sleep/resume process
+*/
+
+static int s3c_pm_enter(suspend_state_t state)
+{
+	unsigned long regs_save[16];
+
+	/* ensure the debug is initialised (if enabled) */
+
+	s3c_pm_debug_init();
+
+	S3C_PMDBG("%s(%d)\n", __func__, state);
+
+	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
+		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
+		return -EINVAL;
+	}
+
+	/* check if we have anything to wake-up with... bad things seem
+	 * to happen if you suspend with no wakeup (system will often
+	 * require a full power-cycle)
+	*/
+
+	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
+		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
+		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
+		return -EINVAL;
+	}
+
+	/* store the physical address of the register recovery block */
+
+	s3c_sleep_save_phys = virt_to_phys(regs_save);
+
+	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
+
+	/* save all necessary core registers not covered by the drivers */
+
+	s3c_pm_save_gpios();
+	s3c_pm_save_uarts();
+	s3c_pm_save_core();
+
+	/* set the irq configuration for wake */
+
+	s3c_pm_configure_extint();
+
+	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
+	    s3c_irqwake_intmask, s3c_irqwake_eintmask);
+
+	s3c_pm_arch_prepare_irqs();
+
+	/* call cpu specific preparation */
+
+	pm_cpu_prep();
+
+	/* flush cache back to ram */
+
+	flush_cache_all();
+
+	s3c_pm_check_store();
+
+	/* send the cpu to sleep... */
+
+	s3c_pm_arch_stop_clocks();
+
+	/* s3c2410_cpu_save will also act as our return point from when
+	 * we resume as it saves its own register state, so use the return
+	 * code to differentiate return from save and return from sleep */
+
+	if (s3c_cpu_save(regs_save) == 0) {
+		flush_cache_all();
+		pm_cpu_sleep();
+	}
+
+	/* restore the cpu state using the kernel's cpu init code. */
+
+	cpu_init();
+
+	/* restore the system state */
+
+	s3c_pm_restore_core();
+	s3c_pm_restore_uarts();
+	s3c_pm_restore_gpios();
+
+	s3c_pm_debug_init();
+
+	/* check what irq (if any) restored the system */
+
+	s3c_pm_arch_show_resume_irqs();
+
+	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
+
+	s3c_pm_check_restore();
+
+	/* LEDs should now be 1110 */
+	s3c_pm_debug_smdkled(1 << 1, 0);
+
+	/* ok, let's return from sleep */
+
+	S3C_PMDBG("S3C PM Resume (post-restore)\n");
+	return 0;
+}
+
+static int s3c_pm_prepare(void)
+{
+	/* prepare check area if configured */
+
+	s3c_pm_check_prepare();
+	return 0;
+}
+
+static void s3c_pm_finish(void)
+{
+	s3c_pm_check_cleanup();
+}
+
+static struct platform_suspend_ops s3c_pm_ops = {
+	.enter		= s3c_pm_enter,
+	.prepare	= s3c_pm_prepare,
+	.finish		= s3c_pm_finish,
+	.valid		= suspend_valid_only_mem,
+};
+
+/* s3c_pm_init
+ *
+ * Attach the power management functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+
+int __init s3c_pm_init(void)
+{
+	printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
+
+	suspend_set_ops(&s3c_pm_ops);
+	return 0;
+}
diff -urN android_2.6.29_org/arch/arm/plat-s3c/pwm.c android_2.6.29/arch/arm/plat-s3c/pwm.c
--- android_2.6.29_org/arch/arm/plat-s3c/pwm.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/pwm.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,288 @@
+/*
+ * arch/arm/plat-s3c/pwm.c
+ *
+ * Copyright (c) by Javi Roman <javiroman@kernel-labs.org>
+ * 		 for the Openmoko Project.
+ *
+ *     S3C2410A SoC PWM support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <mach/hardware.h>
+#include <plat/regs-timer.h>
+#include <plat/pwm.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_PM
+	static unsigned long standby_reg_tcon;
+	static unsigned long standby_reg_tcfg0;
+	static unsigned long standby_reg_tcfg1;
+#endif
+
+int s3c2410_pwm_disable(struct s3c2410_pwm *pwm)
+{
+	unsigned long tcon;
+
+	/* stop timer */
+	tcon = __raw_readl(S3C2410_TCON);
+	tcon &= 0xffffff00;
+	__raw_writel(tcon, S3C2410_TCON);
+
+	clk_disable(pwm->pclk);
+	clk_put(pwm->pclk);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_disable);
+
+int s3c2410_pwm_init(struct s3c2410_pwm *pwm)
+{
+	pwm->pclk = clk_get(NULL, "timers");
+	if (IS_ERR(pwm->pclk))
+		return PTR_ERR(pwm->pclk);
+
+	clk_enable(pwm->pclk);
+	pwm->pclk_rate = clk_get_rate(pwm->pclk);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_init);
+
+int s3c2410_pwm_enable(struct s3c2410_pwm *pwm)
+{
+	unsigned long tcfg0, tcfg1, tcnt, tcmp;
+
+	/* control registers bits */
+	tcfg1 = __raw_readl(S3C2410_TCFG1);
+	tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+	/* divider & scaler slection */
+	switch (pwm->timerid) {
+	case PWM0:
+		tcfg1 &= ~S3C2410_TCFG1_MUX0_MASK;
+		tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
+		break;
+	case PWM1:
+		tcfg1 &= ~S3C2410_TCFG1_MUX1_MASK;
+		tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
+		break;
+	case PWM2:
+		tcfg1 &= ~S3C2410_TCFG1_MUX2_MASK;
+		tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+		break;
+	case PWM3:
+		tcfg1 &= ~S3C2410_TCFG1_MUX3_MASK;
+		tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+		break;
+	case PWM4:
+		/* timer four is not capable of doing PWM */
+		break;
+	default:
+		clk_disable(pwm->pclk);
+		clk_put(pwm->pclk);
+		return -1;
+	}
+
+	/* divider & scaler values */
+	tcfg1 |= pwm->divider;
+	__raw_writel(tcfg1, S3C2410_TCFG1);
+
+	switch (pwm->timerid) {
+	case PWM0:
+	case PWM1:
+		tcfg0 |= pwm->prescaler;
+		__raw_writel(tcfg0, S3C2410_TCFG0);
+		break;
+	default:
+		if ((tcfg0 | pwm->prescaler) != tcfg0) {
+			printk(KERN_WARNING "not changing prescaler of PWM %u,"
+			       " since it's shared with timer4 (clock tick)\n",
+			       pwm->timerid);
+		}
+		break;
+	}
+
+	/* timer count and compare buffer initial values */
+	tcnt = pwm->counter;
+	tcmp = pwm->comparer;
+
+	__raw_writel(tcnt, S3C2410_TCNTB(pwm->timerid));
+	__raw_writel(tcmp, S3C2410_TCMPB(pwm->timerid));
+
+	/* ensure timer is stopped */
+	s3c2410_pwm_stop(pwm);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_enable);
+
+int s3c2410_pwm_start(struct s3c2410_pwm *pwm)
+{
+	unsigned long tcon;
+
+	tcon = __raw_readl(S3C2410_TCON);
+
+	switch (pwm->timerid) {
+	case PWM0:
+		tcon |= S3C2410_TCON_T0START;
+		tcon &= ~S3C2410_TCON_T0MANUALUPD;
+		break;
+	case PWM1:
+		tcon |= S3C2410_TCON_T1START;
+		tcon &= ~S3C2410_TCON_T1MANUALUPD;
+		break;
+	case PWM2:
+		tcon |= S3C2410_TCON_T2START;
+		tcon &= ~S3C2410_TCON_T2MANUALUPD;
+		break;
+	case PWM3:
+		tcon |= S3C2410_TCON_T3START;
+		tcon &= ~S3C2410_TCON_T3MANUALUPD;
+		break;
+	case PWM4:
+		/* timer four is not capable of doing PWM */
+	default:
+		return -ENODEV;
+	}
+
+	__raw_writel(tcon, S3C2410_TCON);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_start);
+
+int s3c2410_pwm_stop(struct s3c2410_pwm *pwm)
+{
+	unsigned long tcon;
+
+	tcon = __raw_readl(S3C2410_TCON);
+
+	switch (pwm->timerid) {
+	case PWM0:
+		tcon &= ~0x00000000;
+		tcon |= S3C2410_TCON_T0RELOAD;
+		tcon |= S3C2410_TCON_T0MANUALUPD;
+		break;
+	case PWM1:
+		tcon &= ~0x00000080;
+		tcon |= S3C2410_TCON_T1RELOAD;
+		tcon |= S3C2410_TCON_T1MANUALUPD;
+		break;
+	case PWM2:
+		tcon &= ~0x00000800;
+		tcon |= S3C2410_TCON_T2RELOAD;
+		tcon |= S3C2410_TCON_T2MANUALUPD;
+		break;
+	case PWM3:
+		tcon &= ~0x00008000;
+		tcon |= S3C2410_TCON_T3RELOAD;
+		tcon |= S3C2410_TCON_T3MANUALUPD;
+		break;
+	case PWM4:
+		/* timer four is not capable of doing PWM */
+	default:
+		return -ENODEV;
+	}
+
+	__raw_writel(tcon, S3C2410_TCON);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_stop);
+
+int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *pwm)
+{
+	__raw_writel(reg_value, S3C2410_TCMPB(pwm->timerid));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_duty_cycle);
+
+int s3c2410_pwm_dumpregs(void)
+{
+	printk(KERN_INFO "TCON: %08lx, TCFG0: %08lx, TCFG1: %08lx\n",
+			(unsigned long)	__raw_readl(S3C2410_TCON),
+			(unsigned long)	__raw_readl(S3C2410_TCFG0),
+			(unsigned long)	__raw_readl(S3C2410_TCFG1));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_dumpregs);
+
+static int __init s3c24xx_pwm_probe(struct platform_device *pdev)
+{
+	struct s3c24xx_pwm_platform_data *pdata = pdev->dev.platform_data;
+
+	dev_info(&pdev->dev, "s3c24xx_pwm is registered \n");
+
+	/* if platform was interested, give him a chance to register
+	 * platform devices that switch power with us as the parent
+	 * at registration time -- ensures suspend / resume ordering
+	 */
+	if (pdata)
+		if (pdata->attach_child_devices)
+			(pdata->attach_child_devices)(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c24xx_pwm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	/* PWM config should be kept in suspending */
+	standby_reg_tcon = __raw_readl(S3C2410_TCON);
+	standby_reg_tcfg0 = __raw_readl(S3C2410_TCFG0);
+	standby_reg_tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+	return 0;
+}
+
+static int s3c24xx_pwm_resume(struct platform_device *pdev)
+{
+	__raw_writel(standby_reg_tcon, S3C2410_TCON);
+	__raw_writel(standby_reg_tcfg0, S3C2410_TCFG0);
+	__raw_writel(standby_reg_tcfg1, S3C2410_TCFG1);
+
+	return 0;
+}
+#else
+#define s3c24xx_pwm_suspend	NULL
+#define s3c24xx_pwm_resume	NULL
+#endif
+
+static struct platform_driver s3c24xx_pwm_driver = {
+	.driver = {
+		.name	= "s3c24xx_pwm",
+		.owner	= THIS_MODULE,
+	},
+	.probe	 = s3c24xx_pwm_probe,
+	.suspend = s3c24xx_pwm_suspend,
+	.resume	 = s3c24xx_pwm_resume,
+};
+
+static int __init s3c24xx_pwm_init(void)
+{
+	return platform_driver_register(&s3c24xx_pwm_driver);
+}
+
+static void __exit s3c24xx_pwm_exit(void)
+{
+}
+
+MODULE_AUTHOR("Javi Roman <javiroman@kernel-labs.org>");
+MODULE_LICENSE("GPL");
+
+module_init(s3c24xx_pwm_init);
+module_exit(s3c24xx_pwm_exit);
diff -urN android_2.6.29_org/arch/arm/plat-s3c/time.c android_2.6.29/arch/arm/plat-s3c/time.c
--- android_2.6.29_org/arch/arm/plat-s3c/time.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c/time.c	2009-04-10 11:13:25.000000000 +0900
@@ -97,7 +97,7 @@
  * IRQs are disabled before entering here from do_gettimeofday()
  */
 
-static unsigned long s3c2410_gettimeoffset (void)
+unsigned long s3c2410_gettimeoffset (void)
 {
 	unsigned long tdone;
 	unsigned long tval;
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/Kconfig android_2.6.29/arch/arm/plat-s3c64xx/Kconfig
--- android_2.6.29_org/arch/arm/plat-s3c64xx/Kconfig	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -19,6 +19,8 @@
 	select S3C_GPIO_PULL_UPDOWN
 	select S3C_GPIO_CFG_S3C24XX
 	select S3C_GPIO_CFG_S3C64XX
+	select USB_ARCH_HAS_OHCI
+	select S3C64XX_SETUP_USBOTG
 	help
 	  Base platform code for any Samsung S3C64XX device
 
@@ -38,6 +40,10 @@
 	  Common clock support code for the S3C6400 that is shared
 	  by other CPUs in the series, such as the S3C6410.
 
+config S3C64XX_DMA
+	bool "S3C64XX DMA"
+	select S3C_DMA
+
 # platform specific device setup
 
 config S3C64XX_SETUP_I2C0
@@ -59,4 +65,10 @@
 	help
 	  Common setup code for S3C64XX with an 24bpp RGB display helper.
 
+config S3C64XX_SETUP_USBOTG
+	bool
+	help
+	  Common setup code for S3C64XX with USB OTG
+
+
 endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/Makefile android_2.6.29/arch/arm/plat-s3c64xx/Makefile
--- android_2.6.29_org/arch/arm/plat-s3c64xx/Makefile	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/Makefile	2009-04-10 11:13:25.000000000 +0900
@@ -12,7 +12,7 @@
 
 # Core files
 
-obj-y				+= dev-uart.o
+obj-y				+= dev-uart.o devs.o
 obj-y				+= cpu.o
 obj-y				+= irq.o
 obj-y				+= irq-eint.o
@@ -24,8 +24,22 @@
 obj-$(CONFIG_CPU_S3C6400_INIT)	+= s3c6400-init.o
 obj-$(CONFIG_CPU_S3C6400_CLOCK)	+= s3c6400-clock.o
 
+# DMA support
+
+obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
+
+# PM support
+
+obj-$(CONFIG_PM)		+= pm.o
+obj-$(CONFIG_PM)		+= sleep.o
+obj-$(CONFIG_PM)		+= irq-pm.o
+
+obj-$(CONFIG_CPU_FREQ_S3C64XX)	+= cpufreq.o
+
 # Device setup
 
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
+obj-$(CONFIG_S3C64XX_SETUP_USBOTG) += dev-usbgadget.o
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/clock.c android_2.6.29/arch/arm/plat-s3c64xx/clock.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/clock.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/clock.c	2009-04-10 11:13:25.000000000 +0900
@@ -27,6 +27,12 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 
+struct clk clk_h2 = {
+	.name		= "hclk2",
+	.id		= -1,
+	.rate		= 0,
+};
+
 struct clk clk_27m = {
 	.name		= "clk_27m",
 	.id		= -1,
@@ -83,7 +89,7 @@
 	return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
 }
 
-static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
+int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
 {
 	return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
 }
@@ -152,6 +158,30 @@
 		.parent		= &clk_48m,
 		.enable		= s3c64xx_sclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_SCLK_MMC2_48,
+	}, {
+		.name		= "dma0",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_DMA0,
+	}, {
+		.name		= "dma1",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_DMA1,
+	}, {
+		.name		= "dma2",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SDMA0,
+	}, {
+		.name		= "dma3",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SDMA1,
 	},
 };
 
@@ -246,9 +276,10 @@
 	&clk_epll,
 	&clk_27m,
 	&clk_48m,
+	&clk_h2,
 };
 
-void __init s3c64xx_register_clocks(void)
+void s3c64xx_register_clocks(void)
 {
 	struct clk *clkp;
 	int ret;
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/cpu.c android_2.6.29/arch/arm/plat-s3c64xx/cpu.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/cpu.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/cpu.c	2009-04-10 11:13:25.000000000 +0900
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -96,9 +97,34 @@
 		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	},
+	}, {
+		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
+		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual 	= (unsigned long)S3C_VA_TZIC0,
+		.pfn		= __phys_to_pfn(S3C64XX_PA_TZIC0),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_TZIC1,
+		.pfn		= __phys_to_pfn(S3C64XX_PA_TZIC1),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}
 };
 
+
+struct sysdev_class s3c64xx_sysclass = {
+	.name	= "s3c64xx-core",
+};
+
+static struct sys_device s3c64xx_sysdev = {
+	.cls	= &s3c64xx_sysclass,
+};
+
+
 /* read cpu identification code */
 
 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
@@ -112,3 +138,11 @@
 	idcode = __raw_readl(S3C_VA_SYS + 0x118);
 	s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
+
+static __init int s3c64xx_sysdev_init(void)
+{
+	sysdev_class_register(&s3c64xx_sysclass);
+	return sysdev_register(&s3c64xx_sysdev);
+}
+
+core_initcall(s3c64xx_sysdev_init);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/cpufreq.c android_2.6.29/arch/arm/plat-s3c64xx/cpufreq.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/cpufreq.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/cpufreq.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,225 @@
+/* linux/arch/arm/plat-s3c64xx/cpufreq.c
+ *
+ * Copyright 2009 Wolfson Microelectronics plc
+ *
+ * S3C64XX CPUfreq Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/cpu.h>
+
+static struct clk *armclk;
+static struct regulator *vddarm;
+
+struct s3c64xx_dvfs {
+	unsigned int vddarm_min;
+	unsigned int vddarm_max;
+};
+
+static struct s3c64xx_dvfs s3c6410_dvfs_table[] = {
+	[0] = { 1000000, 1000000 },
+	[1] = { 1000000, 1050000 },
+	[2] = { 1050000, 1100000 },
+	[3] = { 1050000, 1150000 },
+	[4] = { 1250000, 1350000 },
+};
+
+static struct cpufreq_frequency_table s3c6410_freq_table[] = {
+	{ 0,  66000 },
+	{ 0, 133000 },
+	{ 1, 222000 },
+	{ 1, 266000 },
+	{ 2, 333000 },
+	{ 2, 400000 },
+	{ 3, 532000 },
+	{ 3, 533000 },
+	{ 4, 667000 },
+	{ 0, CPUFREQ_TABLE_END },
+};
+
+/* Data tables for current CPU and maximum index into it */
+static struct cpufreq_frequency_table *s3c64xx_freq_table;
+static struct s3c64xx_dvfs *s3c64xx_dvfs_table;
+
+static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
+{
+	if (policy->cpu != 0)
+		return -EINVAL;
+
+	return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
+}
+
+static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
+{
+	if (cpu != 0)
+		return 0;
+
+	return clk_get_rate(armclk) / 1000;
+}
+
+static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
+				      unsigned int target_freq,
+				      unsigned int relation)
+{
+	int ret = 0;
+	unsigned int i;
+	struct cpufreq_freqs freqs;
+	struct s3c64xx_dvfs *dvfs;
+
+	ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
+					     target_freq, relation, &i);
+	if (ret != 0)
+		return ret;
+
+	freqs.cpu = 0;
+	freqs.old = clk_get_rate(armclk) / 1000;
+	freqs.new = s3c64xx_freq_table[i].frequency;
+	freqs.flags = 0;
+	dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
+
+	if (freqs.old == freqs.new)
+		return 0;
+
+	pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+#ifdef CONFIG_REGULATOR
+	if (vddarm && freqs.new > freqs.old) {
+		ret = regulator_set_voltage(vddarm,
+					    dvfs->vddarm_min,
+					    dvfs->vddarm_max);
+		if (ret != 0) {
+			pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+			       freqs.new, ret);
+			goto err;
+		}
+	}
+#endif
+
+	ret = clk_set_rate(armclk, freqs.new * 1000);
+	if (ret < 0) {
+		pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
+		       freqs.new, ret);
+		goto err;
+	}
+
+#ifdef CONFIG_REGULATOR
+	if (vddarm && freqs.new < freqs.old) {
+		ret = regulator_set_voltage(vddarm,
+					    dvfs->vddarm_min,
+					    dvfs->vddarm_max);
+		if (ret != 0) {
+			pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+			       freqs.new, ret);
+			goto err_clk;
+		}
+	}
+#endif
+
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+	pr_debug("cpufreq: Set actual frequency %lukHz\n",
+		 clk_get_rate(armclk) / 1000);
+
+	return 0;
+
+err_clk:
+	if (clk_set_rate(armclk, freqs.old * 1000) < 0)
+		pr_err("Failed to restore original clock rate\n");
+err:
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+	return ret;
+}
+
+
+static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
+{
+	int ret;
+	struct cpufreq_frequency_table *freq;;
+
+	if (policy->cpu != 0)
+		return -EINVAL;
+
+	if (cpu_is_s3c6410()) {
+		s3c64xx_freq_table = s3c6410_freq_table;
+		s3c64xx_dvfs_table = s3c6410_dvfs_table;
+	}
+
+	if (s3c64xx_freq_table == NULL) {
+		pr_err("cpufreq: No frequency information for this CPU\n");
+		return -ENODEV;
+	}
+
+	armclk = clk_get(NULL, "armclk");
+	if (IS_ERR(armclk)) {
+		pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
+		       PTR_ERR(armclk));
+		return PTR_ERR(armclk);
+	}
+
+#ifdef CONFIG_REGULATOR
+	vddarm = regulator_get(NULL, "vddarm");
+	if (IS_ERR(vddarm)) {
+		ret = PTR_ERR(vddarm);
+		pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
+		pr_err("cpufreq: Only frequency scaling available\n");
+		vddarm = NULL;
+	}
+#endif
+
+	/* Check for frequencies we can generate */
+	freq = s3c64xx_freq_table;
+	while (freq->frequency != CPUFREQ_TABLE_END) {
+		unsigned long r;
+
+		r = clk_round_rate(armclk, freq->frequency * 1000);
+		r /= 1000;
+
+		if (r != freq->frequency)
+			freq->frequency = CPUFREQ_ENTRY_INVALID;
+
+		freq++;
+	}
+
+	policy->cur = clk_get_rate(armclk) / 1000;
+	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+
+	ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
+	if (ret == 0)
+		return ret;
+
+	pr_err("cpufreq: Failed to configure frequency table: %d\n", ret);
+
+	regulator_put(vddarm);
+	clk_put(armclk);
+	return ret;
+}
+
+static struct cpufreq_driver s3c64xx_cpufreq_driver = {
+	.owner		= THIS_MODULE,
+	.flags          = 0,
+	.verify		= s3c64xx_cpufreq_verify_speed,
+	.target		= s3c64xx_cpufreq_set_target,
+	.get		= s3c64xx_cpufreq_get_speed,
+	.init		= s3c64xx_cpufreq_driver_init,
+	.name		= "s3c64xx",
+};
+
+static int __init s3c64xx_cpufreq_init(void)
+{
+	return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
+}
+module_init(s3c64xx_cpufreq_init);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/dev-usbgadget.c android_2.6.29/arch/arm/plat-s3c64xx/dev-usbgadget.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/dev-usbgadget.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/dev-usbgadget.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,32 @@
+/* Base S3C64XX usbgadget resource and device definitions */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/ioport.h>
+
+#include <mach/map.h>
+#include <plat/map-base.h>
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+static struct resource s3c_usbgadget_resource[] = {
+	[0] = {
+		.start = S3C64XX_PA_OTG,
+		.end   = S3C64XX_PA_OTG + 0x200000  - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_OTG,
+		.end   = IRQ_OTG,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+struct platform_device s3c_device_usbgadget = {
+	.name		  = "s3c-otg-usbgadget",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_usbgadget_resource),
+	.resource	  = s3c_usbgadget_resource,
+};
+EXPORT_SYMBOL(s3c_device_usbgadget);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/devs.c android_2.6.29/arch/arm/plat-s3c64xx/devs.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/devs.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/devs.c	2009-04-16 20:14:32.000000000 +0900
@@ -0,0 +1,165 @@
+/* linux/arch/arm/plat-s3c64xx/devs.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * Base S3C64XX resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+#include <plat/adc.h>
+
+/* SMC9115 LAN via ROM interface */
+#if 0
+static struct resource s3c_smc911x_resources[] = {
+      [0] = {
+              .start  = S3C64XX_PA_SMC9115,
+              .end    = S3C64XX_PA_SMC9115 + 0x1fffffff,
+              .flags  = IORESOURCE_MEM,
+      },
+      [1] = {
+              .start = IRQ_EINT(10),
+              .end   = IRQ_EINT(10),
+              .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_smc911x = {
+      .name           = "smc911x",
+      .id             =  -1,
+      .num_resources  = ARRAY_SIZE(s3c_smc911x_resources),
+      .resource       = s3c_smc911x_resources,
+};
+#endif
+/* NAND Controller */
+
+static struct resource s3c_nand_resource[] = {
+	[0] = {
+		.start = S3C64XX_PA_NAND,
+		.end   = S3C64XX_PA_NAND + S3C64XX_SZ_NAND - 1,
+		.flags = IORESOURCE_MEM,
+	}
+};
+
+struct platform_device s3c_device_nand = {
+	.name		  = "s3c-nand",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_nand_resource),
+	.resource	  = s3c_nand_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_nand);
+
+#if 0
+/* USB Device (Gadget)*/
+
+static struct resource s3c_usbgadget_resource[] = {
+	[0] = {
+		.start = S3C_PA_OTG,
+		.end   = S3C_PA_OTG+S3C_SZ_OTG - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_OTG,
+		.end   = IRQ_OTG,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+struct platform_device s3c_device_usbgadget = {
+	.name		  = "s3c2410-usbgadget",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_usbgadget_resource),
+	.resource	  = s3c_usbgadget_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_usbgadget);
+
+/* LCD Controller */
+
+static struct resource s3c_lcd_resource[] = {
+	[0] = {
+		.start = S3C64XX_PA_LCD,
+		.end   = S3C64XX_PA_LCD + SZ_1M - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_LCD_VSYNC ,
+		.end   = IRQ_LCD_SYSTEM,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_lcd = {
+	.name		  = "s3c-lcd",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_lcd_resource),
+	.resource	  = s3c_lcd_resource,
+	.dev              = {
+		.dma_mask		= &s3c_device_lcd_dmamask,
+		.coherent_dma_mask	= 0xffffffffUL
+	}
+};
+#endif
+/* ADC */
+static struct resource s3c_adc_resource[] = {
+	[0] = {
+		.start = S3C_PA_ADC,
+		.end   = S3C_PA_ADC + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_PENDN,
+		.end   = IRQ_PENDN,
+		.flags = IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start = IRQ_ADC,
+		.end   = IRQ_ADC,
+		.flags = IORESOURCE_IRQ,
+	}
+
+};
+
+struct platform_device s3c_device_adc = {
+	.name		  = "s3c-adc",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(s3c_adc_resource),
+	.resource	  = s3c_adc_resource,
+};
+
+void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd)
+{
+	struct s3c_adc_mach_info *npd;
+
+//	npd = kmalloc(sizeof(*npd), GFP_KERNEL);
+	npd = kmemdup(pd, sizeof(struct s3c_adc_mach_info), GFP_KERNEL);
+	if (npd) {
+		memcpy(npd, pd, sizeof(*npd));
+		s3c_device_adc.dev.platform_data = npd;
+	} else {
+		printk(KERN_ERR "no memory for ADC platform data\n");
+	}
+}
+
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/dma-fake.c android_2.6.29/arch/arm/plat-s3c64xx/dma-fake.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/dma-fake.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/dma-fake.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,36 @@
+/* linux/arch/arm/plat-s3c64xx/dma.c
+ *
+ * Copyright 2009 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX DMA core - fake
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+
+
+int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
+{
+	return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_ctrl);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/dma.c android_2.6.29/arch/arm/plat-s3c64xx/dma.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/dma.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/dma.c	2009-04-20 11:36:51.000000000 +0900
@@ -0,0 +1,727 @@
+/* linux/arch/arm/plat-s3c64xx/dma.c
+ *
+ * Copyright 2009 Openmoko, Inc.
+ * Copyright 2009 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/dmapool.h>
+#include <linux/sysdev.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+#include <plat/dma-plat.h>
+
+#include <plat/pl080.h>
+#include <mach/map.h>
+#include <plat/regs-sys.h>
+
+//#undef pr_debug
+//#define pr_debug(x...) printk(x)
+
+/* dma channel state information */
+
+
+struct s3c64xx_dmac {
+	struct sys_device	 sysdev;
+	struct clk		*clk;
+	void __iomem		*regs;
+	struct s3c2410_dma_chan *channels;
+	enum dma_ch		 chanbase;
+};
+
+/* pool to provide LLI buffers */
+static struct dma_pool *dma_pool;
+
+/* Debug configuration and code */
+
+static unsigned char debug_show_buffs = 0;
+
+static void dbg_showchan(struct s3c2410_dma_chan *chan)
+{
+	pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
+		 chan->number,
+		 readl(chan->regs + PL080_CH_SRC_ADDR),
+		 readl(chan->regs + PL080_CH_DST_ADDR),
+		 readl(chan->regs + PL080_CH_LLI),
+		 readl(chan->regs + PL080_CH_CONTROL),
+		 readl(chan->regs + PL080S_CH_CONTROL2),
+		 readl(chan->regs + PL080S_CH_CONFIG));
+}
+
+static void show_lli(struct pl080_lli *lli)
+{
+	pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
+		 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
+		 lli->control0, lli->control1);
+}
+
+static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
+{
+	struct s3c64xx_dma_buff *ptr;
+	struct s3c64xx_dma_buff *end;
+
+	pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
+		 chan->number, chan->next, chan->curr, chan->end);
+
+	ptr = chan->next;
+	end = chan->end;
+
+	if (debug_show_buffs) {
+		for (; ptr != NULL; ptr = ptr->next) {
+			pr_debug("DMA%d: %08x ",
+				 chan->number, ptr->lli_dma);
+			show_lli(ptr->lli);
+		}
+	}
+}
+
+/* End of Debug */
+
+static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
+{
+	struct s3c2410_dma_chan *chan;
+	unsigned int start, offs;
+
+	start = 0;
+
+	if (channel >= DMACH_PCM1_TX)
+		start = 8;
+
+	for (offs = 0; offs < 8; offs++) {
+		chan = &s3c2410_chans[start + offs];
+		pr_debug("dma%d(in %d): %s: in_use=%d\n", chan->number, channel, __func__, chan->in_use);
+		if (!chan->in_use)
+			goto found;
+	}
+
+	return NULL;
+
+found:
+	s3c_dma_chan_map[channel] = chan;
+	return chan;
+}
+
+int s3c2410_dma_config(unsigned int channel, int xferunit)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+	if (chan == NULL)
+		return -EINVAL;
+
+	switch (xferunit) {
+	case 1:
+		chan->hw_width = 0;
+		break;
+	case 2:
+		chan->hw_width = 1;
+		break;
+	case 4:
+		chan->hw_width = 2;
+		break;
+	default:
+		printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_config);
+
+static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
+				 struct pl080_lli *lli,
+				 dma_addr_t data, int size)
+{
+	dma_addr_t src, dst;
+	u32 control0, control1;
+
+	switch (chan->source) {
+	case S3C2410_DMASRC_HW:
+		src = chan->dev_addr;
+		dst = data;
+		control0 = PL080_CONTROL_SRC_AHB2;
+		control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
+		control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
+		control0 |= PL080_CONTROL_DST_INCR;
+		break;
+
+	case S3C2410_DMASRC_MEM:
+		src = data;
+		dst = chan->dev_addr;
+		control0 = PL080_CONTROL_DST_AHB2;
+		control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
+		control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
+		control0 |= PL080_CONTROL_SRC_INCR;
+		break;
+	default:
+		BUG();
+	}
+
+	/* todo - burst control */
+
+	control1 = size / 4; /* TODO - calculate */
+	control0 |= PL080_CONTROL_PROT_SYS;	/* always in priv. mode */
+	control0 |= PL080_CONTROL_TC_IRQ_EN;	/* always fire IRQ */
+
+	lli->src_addr = src;
+	lli->dst_addr = dst;
+	lli->next_lli = 0;
+	lli->control0 = control0;
+	lli->control1 = control1;
+}
+
+static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
+				struct pl080_lli *lli)
+{
+	void __iomem *regs = chan->regs;
+
+	pr_debug("%s: LLI %p => regs\n", __func__, lli);
+	show_lli(lli);
+
+	writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
+	writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
+	writel(lli->next_lli, regs + PL080_CH_LLI);
+	writel(lli->control0, regs + PL080_CH_CONTROL);
+	writel(lli->control1, regs + PL080S_CH_CONTROL2);
+}
+
+static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
+{
+	struct s3c64xx_dmac *dmac = chan->dmac;
+	u32 config;
+	u32 bit = chan->bit;
+
+	dbg_showchan(chan);
+
+	pr_debug("%s: clearing interrupts\n", __func__);
+
+	/* clear interrupts */
+	writel(bit, dmac->regs + PL080_TC_CLEAR);
+	writel(bit, dmac->regs + PL080_ERR_CLEAR);
+
+	pr_debug("%s: starting channel\n", __func__);
+
+	config = readl(chan->regs + PL080S_CH_CONFIG);
+	config |= PL080_CONFIG_ENABLE;
+
+	pr_debug("%s: writing config %08x\n", __func__, config);
+	writel(config, chan->regs + PL080S_CH_CONFIG);
+
+	return 0;
+}
+
+static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
+{
+	u32 config;
+	int timeout;
+
+	pr_debug("%s: stopping channel\n", __func__);
+
+	dbg_showchan(chan);
+
+	config = readl(chan->regs + PL080S_CH_CONFIG);
+	config |= PL080_CONFIG_HALT;
+	writel(config, chan->regs + PL080S_CH_CONFIG);
+
+	timeout = 1000;
+	do {
+		config = readl(chan->regs + PL080S_CH_CONFIG);
+		pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
+		if (config & PL080_CONFIG_ACTIVE)
+			udelay(100);
+		else
+			break;
+		} while (--timeout > 0);
+
+	if (config & PL080_CONFIG_ACTIVE) {
+		printk(KERN_ERR "%s: channel still active\n", __func__);
+		return -EFAULT;
+	}
+
+	config = readl(chan->regs + PL080S_CH_CONFIG);
+	config &= ~PL080_CONFIG_ENABLE;
+	writel(config, chan->regs + PL080S_CH_CONFIG);
+
+	return 0;
+}
+
+static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
+					 struct s3c64xx_dma_buff *buf,
+					 enum s3c2410_dma_buffresult result)
+{
+	if (chan->callback_fn != NULL)
+		(chan->callback_fn)(chan, buf->pw, 0, result);
+}
+
+static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
+{
+	dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
+	kfree(buff);
+}
+
+static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
+{
+	struct s3c64xx_dma_buff *buff, *next;
+	u32 config;
+
+	dbg_showchan(chan);
+
+	pr_debug("%s: flushing channel\n", __func__);
+
+	config = readl(chan->regs + PL080S_CH_CONFIG);
+	config &= ~PL080_CONFIG_ENABLE;
+	writel(config, chan->regs + PL080S_CH_CONFIG);
+
+	/* dump all the buffers associated with this channel */
+
+	for (buff = chan->curr; buff != NULL; buff = next) {
+		next = buff->next;
+		pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
+
+		s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
+		s3c64xx_dma_freebuff(buff);
+	}
+
+	chan->curr = chan->next = chan->end = NULL;
+
+	return 0;
+}
+
+int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+	WARN_ON(!chan);
+	if (!chan)
+		return -EINVAL;
+
+	switch (op) {
+	case S3C2410_DMAOP_START:
+		return s3c64xx_dma_start(chan);
+
+	case S3C2410_DMAOP_STOP:
+		return s3c64xx_dma_stop(chan);
+
+	case S3C2410_DMAOP_FLUSH:
+		return s3c64xx_dma_flush(chan);
+
+	/* belive PAUSE/RESUME are no-ops */
+	case S3C2410_DMAOP_PAUSE:
+	case S3C2410_DMAOP_RESUME:
+	case S3C2410_DMAOP_STARTED:
+	case S3C2410_DMAOP_TIMEOUT:
+		return 0;
+	}
+
+	return -ENOENT;
+}
+EXPORT_SYMBOL(s3c2410_dma_ctrl);
+
+/* s3c2410_dma_enque
+ *
+ */
+
+int s3c2410_dma_enqueue(unsigned int channel, void *id,
+			dma_addr_t data, int size)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+	struct s3c64xx_dma_buff *next;
+	struct s3c64xx_dma_buff *buff;
+	struct pl080_lli *lli;
+	int ret;
+
+	WARN_ON(!chan);
+	if (!chan)
+		return -EINVAL;
+
+	buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_KERNEL);
+	if (!buff) {
+		printk(KERN_ERR "%s: no memory for buffer\n", __func__);
+		return -ENOMEM;
+	}
+
+	lli = dma_pool_alloc(dma_pool, GFP_KERNEL, &buff->lli_dma);
+	if (!lli) {
+		printk(KERN_ERR "%s: no memory for lli\n", __func__);
+		ret = -ENOMEM;
+		goto err_buff;
+	}
+
+	pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
+		 __func__, buff, data, lli, (u32)buff->lli_dma, size);
+
+	buff->lli = lli;
+	buff->pw = id;
+
+	s3c64xx_dma_fill_lli(chan, lli, data, size);
+
+	if ((next = chan->next) != NULL) {
+		struct s3c64xx_dma_buff *end = chan->end;
+		struct pl080_lli *endlli = end->lli;
+
+		pr_debug("enquing onto channel\n");
+
+		end->next = buff;
+		endlli->next_lli = buff->lli_dma;
+
+		if (chan->flags & S3C2410_DMAF_CIRCULAR) {
+			struct s3c64xx_dma_buff *curr = chan->curr;
+			lli->next_lli = curr->lli_dma;
+		}
+
+		if (next == chan->curr) {
+			writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
+			chan->next = buff;
+		}
+
+		show_lli(endlli);
+		chan->end = buff;
+	} else {
+		pr_debug("enquing onto empty channel\n");
+
+		chan->curr = buff;
+		chan->next = buff;
+		chan->end = buff;
+
+		s3c64xx_lli_to_regs(chan, lli);
+	}
+
+	show_lli(lli);
+
+	dbg_showchan(chan);
+	dbg_showbuffs(chan);
+	return 0;
+
+err_buff:
+	kfree(buff);
+	return ret;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_enqueue);
+
+
+int s3c2410_dma_devconfig(int channel,
+			  enum s3c2410_dmasrc source,
+			  unsigned long devaddr)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+	u32 peripheral;
+	u32 config = 0;
+
+	printk("%s: channel %d, source %d, dev %08lx, chan %p\n",
+		 __func__, channel, source, devaddr, chan);
+
+	WARN_ON(!chan);
+	if (!chan)
+		return -EINVAL;
+
+	peripheral = (chan->peripheral & 0xf);
+	chan->source = source;
+	chan->dev_addr = devaddr;
+
+	pr_debug("%s: peripheral %d\n", __func__, peripheral);
+
+	switch (source) {
+	case S3C2410_DMASRC_HW:
+		config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+		config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
+		break;
+	case S3C2410_DMASRC_MEM:
+		config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+		config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
+		break;
+	default:
+		printk(KERN_ERR "%s: bad source\n", __func__);
+		return -EINVAL;
+	}
+
+	/* allow TC and ERR interrupts */
+	config |= PL080_CONFIG_TC_IRQ_MASK;
+	config |= PL080_CONFIG_ERR_IRQ_MASK;
+
+	pr_debug("%s: config %08x\n", __func__, config);
+
+	writel(config, chan->regs + PL080S_CH_CONFIG);
+
+	return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_devconfig);
+
+
+int s3c2410_dma_getposition(unsigned int channel,
+			    dma_addr_t *src, dma_addr_t *dst)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+
+	WARN_ON(!chan);
+	if (!chan)
+		return -EINVAL;
+
+	if (src != NULL)
+ 		*src = readl(chan->regs + PL080_CH_SRC_ADDR);
+
+ 	if (dst != NULL)
+ 		*dst = readl(chan->regs + PL080_CH_DST_ADDR);
+
+ 	return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_getposition);
+
+/* s3c2410_request_dma
+ *
+ * get control of an dma channel
+*/
+
+int s3c2410_dma_request(unsigned int channel,
+			struct s3c2410_dma_client *client,
+			void *dev)
+{
+	struct s3c2410_dma_chan *chan;
+	unsigned long flags;
+
+	pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
+		 channel, client->name, dev);
+
+	local_irq_save(flags);
+
+	chan = s3c64xx_dma_map_channel(channel);
+	if (chan == NULL) {
+		local_irq_restore(flags);
+		return -EBUSY;
+	}
+
+	dbg_showchan(chan);
+
+	chan->client = client;
+	chan->in_use = 1;
+	chan->peripheral = channel;
+
+	local_irq_restore(flags);
+
+	/* need to setup */
+
+	pr_debug("%s: channel initialised, %p\n", __func__, chan);
+
+	return chan->number | DMACH_LOW_LEVEL;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_request);
+
+/* s3c2410_dma_free
+ *
+ * release the given channel back to the system, will stop and flush
+ * any outstanding transfers, and ensure the channel is ready for the
+ * next claimant.
+ *
+ * Note, although a warning is currently printed if the freeing client
+ * info is not the same as the registrant's client info, the free is still
+ * allowed to go through.
+*/
+
+int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
+{
+	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+	unsigned long flags;
+
+	if (chan == NULL)
+		return -EINVAL;
+
+	local_irq_save(flags);
+
+	if (chan->client != client) {
+		printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
+		       channel, chan->client, client);
+	}
+
+	/* sort out stopping and freeing the channel */
+
+
+	chan->client = NULL;
+	chan->in_use = 0;
+
+	if (!(channel & DMACH_LOW_LEVEL))
+		s3c_dma_chan_map[channel] = NULL;
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+EXPORT_SYMBOL(s3c2410_dma_free);
+
+
+static void s3c64xx_dma_tcirq(struct s3c64xx_dmac *dmac, int offs)
+{
+	struct s3c2410_dma_chan *chan = dmac->channels + offs;
+
+	/* note, we currently do not bother to work out which buffer
+	 * or buffers have been completed since the last tc-irq. */
+
+	if (chan->callback_fn)
+		(chan->callback_fn)(chan, chan->curr->pw, 0, S3C2410_RES_OK);
+}
+
+static void s3c64xx_dma_errirq(struct s3c64xx_dmac *dmac, int offs)
+{
+	printk(KERN_DEBUG "%s: offs %d\n", __func__, offs);
+}
+
+static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
+{
+	struct s3c64xx_dmac *dmac = pw;
+	u32 tcstat, errstat;
+	u32 bit;
+	int offs;
+
+	tcstat = readl(dmac->regs + PL080_TC_STATUS);
+	errstat = readl(dmac->regs + PL080_ERR_STATUS);
+
+	for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
+		if (tcstat & bit) {
+			writel(bit, dmac->regs + PL080_TC_CLEAR);
+			s3c64xx_dma_tcirq(dmac, offs);
+		}
+
+		if (errstat & bit) {
+			s3c64xx_dma_errirq(dmac, offs);
+			writel(bit, dmac->regs + PL080_ERR_CLEAR);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct sysdev_class dma_sysclass = {
+	.name		= "s3c64xx-dma",
+};
+
+static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
+			     int irq, unsigned int base)
+{
+	struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
+	struct s3c64xx_dmac *dmac;
+	char clkname[16];
+	void __iomem *regs;
+	void __iomem *regptr;
+	int err, ch;
+
+	dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
+	if (!dmac) {
+		printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
+		return -ENOMEM;
+	}
+
+	dmac->sysdev.id = chno / 8;
+	dmac->sysdev.cls = &dma_sysclass;
+
+	err = sysdev_register(&dmac->sysdev);
+	if (err) {
+		printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
+		goto err_alloc;
+	}
+
+	regs = ioremap(base, 0x200);
+	if (!regs) {
+		printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
+		err = -ENXIO;
+		goto err_dev;
+	}
+
+	snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
+
+	dmac->clk = clk_get(NULL, clkname);
+	if (IS_ERR(dmac->clk)) {
+		printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
+		err = PTR_ERR(dmac->clk);
+		goto err_map;
+	}
+
+	clk_enable(dmac->clk);
+
+	dmac->regs = regs;
+	dmac->chanbase = chbase;
+	dmac->channels = chptr;
+
+	err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
+	if (err < 0) {
+		printk(KERN_ERR "%s: failed to get irq\n", __func__);
+		goto err_clk;
+	}
+
+	regptr = regs + PL080_Cx_BASE(0);
+
+	for (ch = 0; ch < 8; ch++, chno++, chptr++) {
+		printk(KERN_INFO "%s: registering DMA %d (%p)\n",
+		       __func__, chno, regptr);
+
+		chptr->bit = 1 << ch;
+		chptr->number = chno;
+		chptr->dmac = dmac;
+		chptr->regs = regptr;
+		regptr += PL008_Cx_STRIDE;
+	}
+
+	/* for the moment, permanently enable the controller */
+	writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
+
+	printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
+
+	return 0;
+
+err_clk:
+	clk_disable(dmac->clk);
+	clk_put(dmac->clk);
+err_map:
+	iounmap(regs);
+err_dev:
+	sysdev_unregister(&dmac->sysdev);
+err_alloc:
+	kfree(dmac);
+	return err;
+}  
+
+static int __init s3c64xx_dma_init(void)
+{
+	int ret;
+
+	printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
+
+	dma_pool = dma_pool_create("DMA-LLI", NULL, 32, 16, 0);
+	if (!dma_pool) {
+		printk(KERN_ERR "%s: failed to create pool\n", __func__);
+		return -ENOMEM;
+	}
+
+	ret = sysdev_class_register(&dma_sysclass);
+	if (ret) {
+		printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
+		return -ENOMEM;
+	}
+
+	/* Set all DMA configuration to be DMA, not SDMA */
+	writel(0xffffff, S3C_SYSREG(0x110));
+	
+	/* Register standard DMA controlers */
+	s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
+	s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
+
+	return 0;
+}
+
+arch_initcall(s3c64xx_dma_init);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/gpiolib.c android_2.6.29/arch/arm/plat-s3c64xx/gpiolib.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/gpiolib.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/gpiolib.c	2009-04-10 11:13:25.000000000 +0900
@@ -385,12 +385,19 @@
 {
 	chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
 	chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
+	chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
 }
 
 static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
 {
 	chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
 	chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
+	chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
+{
+	chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
 }
 
 static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
@@ -412,9 +419,10 @@
 	s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
 			    s3c64xx_gpiolib_add_4bit2);
 
-	s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
+	s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
+			    s3c64xx_gpiolib_add_2bit);
 
 	return 0;
 }
 
-core_initcall(s3c64xx_gpiolib_init);
+arch_initcall(s3c64xx_gpiolib_init);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/dma-plat.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/dma-plat.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/dma-plat.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
+ *
+ * Copyright 2009 Openmoko, Inc.
+ * Copyright 2009 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
+
+struct s3c64xx_dma_buff;
+
+/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
+ * @next: Pointer to next buffer in queue or ring.
+ * @pw: Client provided identifier
+ * @lli: Pointer to hardware descriptor this buffer is associated with.
+ * @lli_dma: Hardare address of the descriptor.
+ */
+struct s3c64xx_dma_buff {
+	struct s3c64xx_dma_buff *next;
+
+	void			*pw;
+	struct pl080_lli	*lli;
+	dma_addr_t		 lli_dma;
+};
+
+struct s3c64xx_dmac;
+
+struct s3c2410_dma_chan {
+	unsigned char		 number;      /* number of this dma channel */
+	unsigned char		 in_use;      /* channel allocated */
+	unsigned char		 bit;	      /* bit for enable/disable/etc */
+	unsigned char		 hw_width;
+	unsigned char		 peripheral;
+
+	unsigned int		 flags;
+	enum s3c2410_dmasrc	 source;
+
+
+	dma_addr_t		dev_addr;
+
+	struct s3c2410_dma_client *client;
+	struct s3c64xx_dmac	*dmac;		/* pointer to controller */
+
+	void __iomem		*regs;
+
+	/* cdriver callbacks */
+	s3c2410_dma_cbfn_t	 callback_fn;	/* buffer done callback */
+	s3c2410_dma_opfn_t	 op_fn;		/* channel op callback */
+
+	/* buffer list and information */
+	struct s3c64xx_dma_buff	*curr;		/* current dma buffer */
+	struct s3c64xx_dma_buff	*next;		/* next buffer to load */
+	struct s3c64xx_dma_buff	*end;		/* end of queue */
+
+	/* note, when channel is running in circular mode, curr is the
+	 * first buffer enqueued, end is the last and curr is where the
+	 * last buffer-done event is set-at. The buffers are not freed
+	 * and the last buffer hardware descriptor points back to the
+	 * first. 
+	 */
+};
+
+#include <plat/dma-core.h>
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/irqs.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/irqs.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/irqs.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/irqs.h	2009-04-10 11:13:25.000000000 +0900
@@ -117,7 +117,7 @@
 #define IRQ_ONENAND1		S3C64XX_IRQ_VIC1(12)
 #define IRQ_NFC			S3C64XX_IRQ_VIC1(13)
 #define IRQ_CFCON		S3C64XX_IRQ_VIC1(14)
-#define IRQ_USBH		S3C64XX_IRQ_VIC1(15)
+#define IRQ_UHOST		S3C64XX_IRQ_VIC1(15)
 #define IRQ_SPI0		S3C64XX_IRQ_VIC1(16)
 #define IRQ_SPI1		S3C64XX_IRQ_VIC1(17)
 #define IRQ_IIC			S3C64XX_IRQ_VIC1(18)
@@ -148,6 +148,7 @@
 /* compatibility for device defines */
 
 #define IRQ_IIC1		IRQ_S3C6410_IIC1
+#define IRQ_USBH		IRQ_UHOST
 
 /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
  * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
@@ -157,6 +158,7 @@
 
 #define S3C_EINT(x)		((x) + S3C_IRQ_EINT_BASE)
 #define IRQ_EINT(x)		S3C_EINT(x)
+#define IRQ_EINT_BIT(x)		((x) - S3C_EINT(0))
 
 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
  * that they are sourced from the GPIO pins but with a different scheme for
@@ -197,5 +199,6 @@
 
 #define NR_IRQS	(IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 
+#define FIQ_START S3C_IRQ(0)
 #endif /* __ASM_PLAT_S3C64XX_IRQS_H */
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/pl080.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/pl080.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/pl080.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/pl080.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,110 @@
+/* arch/arm/include/asm/hardware/pl080.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ARM PrimeCell PL080 DMA controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Note, there are some Samsung updates to this controller block which
+ * make it not entierly compatible with the PL080 specification from
+ * ARM. When in doubt, check the Samsung documentation first.
+ *
+ * The Samsung defines are PL080S, and add an extra controll register,
+ * the ability to move more than 2^11 counts of data and some extra
+ * OneNAND features.
+*/
+
+#define PL080_INT_STATUS			(0x00)
+#define PL080_TC_STATUS				(0x04)
+#define PL080_TC_CLEAR				(0x08)
+#define PL080_ERR_STATUS			(0x0C)
+#define PL080_ERR_CLEAR				(0x10)
+#define PL080_RAW_TC_STATUS			(0x14)
+#define PL080_RAW_ERR_STATUS			(0x18)
+#define PL080_EN_CHAN				(0x1c)
+#define PL080_SOFT_BREQ				(0x20)
+#define PL080_SOFT_SREQ				(0x24)
+#define PL080_SOFT_LBREQ			(0x28)
+#define PL080_SOFT_LSREQ			(0x2C)
+
+#define PL080_CONFIG				(0x30)
+#define PL080_CONFIG_M2_BE			(1 << 2)
+#define PL080_CONFIG_M1_BE			(1 << 1)
+#define PL080_CONFIG_ENABLE			(1 << 0)
+
+#define PL080_SYNC				(0x34)
+
+/* Per channel configuration registers */
+
+#define PL008_Cx_STRIDE				(0x20)
+#define PL080_Cx_BASE(x)			((0x100 + (x * 0x20)))
+#define PL080_Cx_SRC_ADDR(x)			((0x100 + (x * 0x20)))
+#define PL080_Cx_DST_ADDR(x)			((0x104 + (x * 0x20)))
+#define PL080_Cx_LLI(x)				((0x108 + (x * 0x20)))
+#define PL080_Cx_CONTROL(x)			((0x10C + (x * 0x20)))
+#define PL080_Cx_CONFIG(x)			((0x110 + (x * 0x20)))
+#define PL080S_Cx_CONTROL2(x)			((0x110 + (x * 0x20)))
+#define PL080S_Cx_CONFIG(x)			((0x114 + (x * 0x20)))
+
+#define PL080_CH_SRC_ADDR			(0x00)
+#define PL080_CH_DST_ADDR			(0x04)
+#define PL080_CH_LLI				(0x08)
+#define PL080_CH_CONTROL			(0x0C)
+#define PL080_CH_CONFIG				(0x10)
+#define PL080S_CH_CONTROL2			(0x10)
+#define PL080S_CH_CONFIG			(0x14)
+
+#define PL080_LLI_ADDR_MASK			(0x3fffffff << 2)
+#define PL080_LLI_ADDR_SHIFT			(2)
+#define PL080_LLI_LM_AHB2			(1 << 0)
+
+#define PL080_CONTROL_TC_IRQ_EN			(1 << 31)
+#define PL080_CONTROL_PROT_MASK			(0x7 << 28)
+#define PL080_CONTROL_PROT_SHIFT		(28)
+#define PL080_CONTROL_PROT_SYS			(1 << 28)
+#define PL080_CONTROL_DST_INCR			(1 << 27)
+#define PL080_CONTROL_SRC_INCR			(1 << 26)
+#define PL080_CONTROL_DST_AHB2			(1 << 25)
+#define PL080_CONTROL_SRC_AHB2			(1 << 24)
+#define PL080_CONTROL_DWIDTH_MASK		(0x7 << 21)
+#define PL080_CONTROL_DWIDTH_SHIFT		(21)
+#define PL080_CONTROL_SWIDTH_MASK		(0x7 << 18)
+#define PL080_CONTROL_SWIDTH_SHIFT		(18)
+#define PL080_CONTROL_DB_SIZE_MASK		(0x7 << 15)
+#define PL080_CONTROL_DB_SIZE_SHIFT		(15)
+#define PL080_CONTROL_SB_SIZE_MASK		(0x7 << 12)
+#define PL080_CONTROL_SB_SIZE_SHIFT		(12)
+#define PL080_CONTROL_TRANSFER_SIZE_MASK	(0xfff << 0)
+#define PL080_CONTROL_TRANSFER_SIZE_SHIFT	(0)
+
+#define PL080_CONFIG_HALT			(1 << 18)
+#define PL080_CONFIG_ACTIVE			(1 << 17)
+#define PL080_CONFIG_LOCK			(1 << 16)
+#define PL080_CONFIG_TC_IRQ_MASK		(1 << 15)
+#define PL080_CONFIG_ERR_IRQ_MASK		(1 << 14)
+#define PL080_CONFIG_FLOW_CONTROL_MASK		(0x7 << 11)
+#define PL080_CONFIG_FLOW_CONTROL_SHIFT		(11)
+#define PL080_CONFIG_DST_SEL_MASK		(0xf << 6)
+#define PL080_CONFIG_DST_SEL_SHIFT		(6)
+#define PL080_CONFIG_SRC_SEL_MASK		(0xf << 1)
+#define PL080_CONFIG_SRC_SEL_SHIFT		(1)
+#define PL080_CONFIG_ENABLE			(1 << 0)
+
+
+/* DMA linked list chain structure */
+
+struct pl080_lli {
+	u32	src_addr;
+	u32	dst_addr;
+	u32	next_lli;
+	u32	control0;
+	u32	control1;
+};
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/pm-core.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/pm-core.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/pm-core.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/pm-core.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,106 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+	u32 tmp = __raw_readl(S3C_PCLK_GATE);
+
+	/* As a note, since the S3C64XX UARTs generally have multiple
+	 * clock sources, we simply enable PCLK at the moment and hope
+	 * that the resume settings for the UART are suitable for the
+	 * use with PCLK.
+	 */
+
+	tmp |= S3C_CLKCON_PCLK_UART0;
+	tmp |= S3C_CLKCON_PCLK_UART1;
+	tmp |= S3C_CLKCON_PCLK_UART2;
+	tmp |= S3C_CLKCON_PCLK_UART3;
+
+	__raw_writel(tmp, S3C_PCLK_GATE);
+	udelay(10);
+}
+
+static inline void s3c_pm_arch_clear_vic(void __iomem *base)
+{
+	__raw_writel(~0, base + VIC_INT_ENABLE_CLEAR);
+	__raw_writel(~0, base + VIC_INT_SOFT_CLEAR);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+	/* shutdown the VICs */
+	s3c_pm_arch_clear_vic(S3C_VA_VIC0);
+	s3c_pm_arch_clear_vic(S3C_VA_VIC1);
+
+	/* clear any pending EINT0 interrupts */
+	__raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+}
+
+/* make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on */
+
+#define s3c_irqwake_eintallow	((1 << 28) - 1)
+#define s3c_irqwake_intallow	(0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+					   struct pm_uart_save *save)
+{
+	u32 ucon = __raw_readl(regs + S3C2410_UCON);
+	u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+	u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+	u32 new_ucon;
+	u32 delta;
+
+	/* S3C64XX UART blocks only support level interrupts, so ensure that
+	 * when we restore unused UART blocks we force the level interrupt
+	 * settigs. */
+	save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+	/* We have a constraint on changing the clock type of the UART
+	 * between UCLKx and PCLK, so ensure that when we restore UCON
+	 * that the CLK field is correctly modified if the bootloader
+	 * has changed anything.
+	 */
+	if (ucon_clk != save_clk) {
+		new_ucon = save->ucon;
+		delta = ucon_clk ^ save_clk;
+
+		/* change from UCLKx => wrong PCLK,
+		 * either UCLK can be tested for by a bit-test
+		 * with UCLK0 */
+		if (ucon_clk & S3C6400_UCON_UCLK0 &&
+		    !(save_clk & S3C6400_UCON_UCLK0) &&
+		    delta & S3C6400_UCON_PCLK2) {
+			new_ucon &= ~S3C6400_UCON_UCLK0;
+		} else if (delta == S3C6400_UCON_PCLK2) {
+			/* as an precaution, don't change from
+			 * PCLK2 => PCLK or vice-versa */
+			new_ucon ^= S3C6400_UCON_PCLK2;
+		}
+
+		S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+			  ucon, new_ucon, save->ucon);
+		save->ucon = new_ucon;
+	}
+}
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-camif.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-camif.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-camif.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-camif.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,460 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-camif.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef ___ASM_ARCH_REGS_CAMIF_H
+#define ___ASM_ARCH_REGS_CAMIF_H
+
+#define S3C_CAMIFREG(x) (x)
+
+/*************************************************************************
+ * Macro part
+ ************************************************************************/
+#define S3C_CISRCFMT_SOURCEHSIZE(x)			((x) << 16)
+#define S3C_CISRCFMT_GET_SOURCEHSIZE(x)			(((x) >> 16) & 0x1FFFF)
+#define S3C_CISRCFMT_SOURCEVSIZE(x)			((x) << 0)
+#define S3C_CISRCFMT_GET_SOURCEVSIZE(x)			(((x) >> 0) & 0x1FFF)
+
+#define S3C_CIWDOFST_WINHOROFST(x)			((x) << 16)
+#define S3C_CIWDOFST_GET_WINHOROFST(x)			(((x) >> 16) & 0x7FF)
+#define S3C_CIWDOFST_WINVEROFST(x)			((x) << 0)
+#define S3C_CIWDOFST_GET_WINVEROFST(x)			(((x) >> 0) & 0x7FF)
+
+#define S3C_CIDOWSFT2_WINHOROFST2(x)			((x) << 16)
+#define S3C_CIDOWSFT2_GET_WINHOROFST2(x)		(((x) >> 16) & 0x7FF)
+#define S3C_CIDOWSFT2_WINVEROFST2(x)			((x) << 0)
+#define S3C_CIDOWSFT2_GET_WINVEROFST2(x)		(((x) >> 0) & 0x7FF)
+
+#define S3C_CICOTRGFMT_TARGETHSIZE_CO(x)		((x) << 16)
+#define S3C_CICOTRGFMT_GET_TARGETHSIZE_CO(x)		(((x) >> 16) & 0x1FFF)
+
+#define S3C_CICOTRGFMT_TARGETVSIZE_CO(x)		((x) << 0)
+#define S3C_CICOTRGFMT_GET_TARGETVSIZE_CO(x)		(((x) >> 0) & 0x1FFF)
+
+#define S3C_CICOCTRL_YBURST1_CO(x)			((x) << 19)
+#define S3C_CICOCTRL_YBURST2_CO(x)			((x) << 14)
+#define S3C_CICOCTRL_CBURST1_CO(x)			((x) << 9)
+#define S3C_CICOCTRL_CBURST2_CO(x)			((x) << 4)
+
+#define S3C_CICOSCPRERATIO_SHFACTOR_CO(x)		((x) << 28)
+#define S3C_CICOSCPRERATIO_GET_SHFACTOR_CO(x)		(((x) >> 28) & 0x7F)
+#define S3C_CICOSCPRERATIO_PREHORRATIO_CO(x)		((x) << 16)
+#define S3C_CICOSCPRERATIO_GET_PREHORRATIO_CO(x)	(((x) >> 16) & 0x7F)
+#define S3C_CICOSCPRERATIO_PREVERRATIO_CO(x)		((x) << 0)
+#define S3C_CICOSCPRERATIO_GET_PREVERRATIO_CO(x)	(((x) >> 0) & 0x7F)
+
+#define S3C_CICOSCPREDST_PREDSTWIDTH_CO(x)		((x) << 16)
+#define S3C_CICOSCPREDST_GET_PREDSTWIDTH_CO(x)		(((x) >> 16) & 0x7FF)
+#define S3C_CICOSCPREDST_PREDSTHEIGHT_CO(x)		((x) << 0)
+#define S3C_CICOSCPREDST_GET_PREDSTHEIGHT_CO(x)		(((x) >> 0) & 0x7FF)
+
+#define S3C_CICOSCCTRL_MAINHORRATIO_CO(x)		((x) << 16)
+#define S3C_CICOSCCTRL_GET_MAINHORRATIO_CO(x)		(((x) >> 16) & 0x1FF)
+#define S3C_CICOSCCTRL_MAINVERRATIO_CO(x)		((x) << 0)
+
+#define S3C_CICOSTATUS_FRAMECNT_CO(x)			((x) << 26)
+#define S3C_CICOSTATUS_GET_FRAMECNT_CO(x)		(((x) >> 26) & 0x3)
+
+#define S3C_CIPRTRGFMT_TARGETHSIZE_PR(x)		((x) << 16)
+#define S3C_CIPRTRGFMT_GET_TARGETHSIZE_PR(x)		(((x) >> 16) & 0x1FFF)
+
+#define S3C_CIPRTRGFMT_GET_ROT90_PR(x)			(((x) >> 13) & 0x1)
+
+#define S3C_CIPRTRGFMT_TARGETVSIZE_PR(x)		((x) << 0)
+#define S3C_CIPRTRGFMT_GET_TARGETVSIZE_PR(x)		(((x) >> 0) & 0x1FFF)
+
+#define S3C_CIPRSCPRERATIO_SHFACTOR_PR(x)		((x) << 28)
+#define S3C_CIPRSCPRERATIO_GET_SHFACTOR_PR(x)		(((x) >> 28) & 0xF)
+#define S3C_CIPRSCPRERATIO_PREHORRATIO_PR(x)		((x) << 16)
+#define S3C_CIPRSCPRERATIO_GET_PREHORRATIO_PR(x)	(((x) >> 16) & 0x7F)
+#define S3C_CIPRSCPRERATIO_PREVERRATIO_PR(x)		((x) << 0)
+#define S3C_CIPRSCPRERATIO_GET_PREVERRATIO_PR(x)	(((x) >> 0) & 0x7F)
+
+#define S3C_CIPRSCPREDST_PREDSTWIDTH_PR(x)		((x) << 16)
+#define S3C_CIPRSCPREDST_GET_PREDSTWIDTH_PR(x)		(((x) >> 16) & 0xFFF)
+#define S3C_CIPRSCPREDST_PREDSTHEIGHT_PR(x)		((x) << 0)
+#define S3C_CIPRSCPREDST_GET_PREDSTHEIGHT_PR(x)		(((x) >> 0) & 0xFFF)
+
+#define S3C_CIPRSCCTRL_MAINHORRATIO_PR(x)		((x) << 16)
+#define S3C_CIPRSCCTRL_GET_MAINHORRATIO_PR(x)		(((x) >> 16) && 0x1FF)
+#define S3C_CIPRSCCTRL_MAINVERRATIO_PR(x)		((x) << 0)
+#define S3C_CIPRSCCTRL_GET_MAINVERRATIO_PR(x)		(((x) >> 0) && 0x1FF)
+
+/*************************************************************************
+ * Bit definition part
+ ************************************************************************/
+/* Windows Offset Register */
+#define S3C_CIWDOFST_WINOFSEN				(1 << 31)
+#define S3C_CIWDOFST_CLROVCOFIY				(1 << 30)
+#define S3C_CIWDOFST_CLROVRLB_CO			(1 << 29)
+#define S3C_CIWDOFST_CLROVRLB_PR			(1 << 28)
+#define S3C_CIWDOFST_CLROVPRFIY				(1 << 27)
+#define S3C_CIWDOFST_CLROVCOFICB			(1 << 15)
+#define S3C_CIWDOFST_CLROVCOFICR			(1 << 14)
+#define S3C_CIWDOFST_CLROVPRFICB			(1 << 13)
+#define S3C_CIWDOFST_CLROVPRFICR			(1 << 12)
+
+/* Global Control Register */
+#define S3C_CIGCTRL_SWRST				(1 << 31)
+#define S3C_CIGCTRL_CAMRST				(1 << 30)
+
+#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
+#define	S3C_CIGCTRL_IRQ_LEVEL				(1 << 20)
+#endif
+
+#define S3C_CIGCTRL_TESTPATTERN_VER_INC			(3 << 27)
+#define S3C_CIGCTRL_TESTPATTERN_HOR_INC			(2 << 27)
+#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR		(1 << 27)
+#define S3C_CIGCTRL_TESTPATTERN_NORMAL			(0 << 27)
+
+#define S3C_CIGCTRL_INVPOLPCLK				(1 << 26)
+#define S3C_CIGCTRL_INVPOLVSYNC				(1 << 25)
+#define S3C_CIGCTRL_INVPOLHREF				(1 << 24)
+#define S3C_CIGCTRL_IRQ_OVFEN				(1 << 22)
+#define S3C_CIGCTRL_HREF_MASK				(1 << 21)
+#define S3C_CIGCTRL_IRQ_LEVEL				(1 << 20)
+#define S3C_CIGCTRL_IRQ_CLR_C				(1 << 19)
+#define S3C_CIGCTRL_IRQ_CLR_P				(1 << 18)
+
+/* Codec Target Format Register */
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C_CICOTRGFMT_IN422_422			(1 << 31)
+#define S3C_CICOTRGFMT_IN422_420			(0 << 31)
+#define S3C_CICOTRGFMT_OUT422_422			(1 << 30)
+#define S3C_CICOTRGFMT_OUT422_420			(0 << 30)
+
+#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
+#define S3C_CICOTRGFMT_OUTFORMAT_RGBOUT			(3 << 29)
+#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUTINTERLEAVE	(2 << 29)
+#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUT		(1 << 29)
+#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR420OUT		(0 << 29)
+#endif
+
+#define S3C_CICOTRGFMT_INTERLEAVE_ON			(1 << 29)
+#define S3C_CICOTRGFMT_INTERLEAVE_OFF			(0 << 29)
+
+#define S3C_CICOTRGFMT_FLIP_180				(3 << 14)
+#define S3C_CICOTRGFMT_FLIP_Y_MIRROR			(2 << 14)
+#define S3C_CICOTRGFMT_FLIP_X_MIRROR			(1 << 14)
+#define S3C_CICOTRGFMT_FLIP_NORMAL			(0 << 14)
+
+/* Codec DMA Control Register */
+#define S3C_CICOCTRL_LASTIRQEN				(1 << 2)
+#define S3C_CICOCTRL_ORDER422_CRYCBY			(3 << 0)
+#define S3C_CICOCTRL_ORDER422_CBYCRY			(2 << 0)
+#define S3C_CICOCTRL_ORDER422_YCRYCB			(1 << 0)
+#define S3C_CICOCTRL_ORDER422_YCBYCR			(0 << 0)
+
+/* Codec Main-Scaler Control Register */
+#define S3C_CICOSCCTRL_SCALERBYPASS_CO			(1 << 31)
+#define S3C_CICOSCCTRL_SCALEUP_H			(1 << 30)
+#define S3C_CICOSCCTRL_SCALEUP_V			(1 << 29)
+
+#define S3C_CICOSCCTRL_CSCR2Y_WIDE			(1 << 28)
+#define S3C_CICOSCCTRL_CSCR2Y_NARROW			(0 << 28)
+
+#define S3C_CICOSCCTRL_CSCY2R_WIDE			(1 << 27)
+#define S3C_CICOSCCTRL_CSCY2R_NARROW			(0 << 27)
+
+#define S3C_CICOSCCTRL_LCDPATHEN_FIFO			(1 << 26)
+#define S3C_CICOSCCTRL_LCDPATHEN_DMA			(0 << 26)
+
+#define S3C_CICOSCCTRL_INTERLACE_INTERLACE		(1 << 25)
+#define S3C_CICOSCCTRL_INTERLACE_PROGRESSIVE		(0 << 25)
+
+#define S3C_CICOSCCTRL_COSCALERSTART			(1 << 15)
+
+#define S3C_CICOSCCTRL_INRGB_FMT_RGB888			(2 << 13)
+#define S3C_CICOSCCTRL_INRGB_FMT_RGB666			(1 << 13)
+#define S3C_CICOSCCTRL_INRGB_FMT_RGB565			(0 << 13)
+
+#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB888		(2 << 11)
+#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB666		(1 << 11)
+#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB565		(0 << 11)
+
+#define S3C_CICOSCCTRL_EXTRGB_EXTENSION			(1 << 10)
+#define S3C_CICOSCCTRL_EXTRGB_NORMAL			(0 << 10)
+
+/* Codec Status Register */
+#define S3C_CICOSTATUS_OVFIY_CO				(1 << 31)
+#define S3C_CICOSTATUS_OVFICB_CO			(1 << 30)
+#define S3C_CICOSTATUS_OVFICR_CO			(1 << 29)
+#define S3C_CICOSTATUS_VSYNC				(1 << 28)
+#define S3C_CICOSTATUS_WINOFSTEN_CO			(1 << 25)
+#define S3C_CICOSTATUS_IMGCPTEN_CAMIF			(1 << 22)
+#define S3C_CICOSTATUS_IMGCPTEN_COSC			(1 << 21)
+#define S3C_CICOSTATUS_VSYNC_A				(1 << 20)
+#define S3C_CICOSTATUS_VSYNC_B				(1 << 19)
+#define S3C_CICOSTATUS_OVRLB_CO				(1 << 18)
+#define S3C_CICOSTATUS_FRAMEEND_CO			(1 << 17)
+
+/* Preview Target Format Register */
+#define S3C_CIPRTRGFMT_FLIPMD_180ROT			(3 << 14)
+#define S3C_CIPRTRGFMT_FLIPMD_YMIRROR			(2 << 14)
+#define S3C_CIPRTRGFMT_FLIPMD_XMIRROR			(1 << 14)
+#define S3C_CIPRTRGFMT_FLIPMD_NORMAL			(0 << 14)
+
+#define S3C_CIPRTRGFMT_ROT90_ROTATE			(1 << 13)
+#define S3C_CIPRTRGFMT_ROT90_BYPASS			(0 << 13)
+
+/* Preview DMA Control Register */
+#define S3C_CIPRCTRL_LASTIRQEN_ENABLE			(1 << 2)
+#define S3C_CIPRCTRL_LASTIRQEN_NORMAL			(0 << 2)
+
+#define S3C_CIPRCTRL_ORDER422_CRYCBY			(3 << 0)
+#define S3C_CIPRCTRL_ORDER422_CBYCRY			(2 << 0)
+#define S3C_CIPRCTRL_ORDER422_YCRYCB			(1 << 0)
+#define S3C_CIPRCTRL_ORDER422_YCBYCR			(0 << 0)
+
+/* Preview Main-Scaler Control Register */
+#define S3C_CIPRSCCTRL_SAMPLE_PR			(1 << 31)
+
+#define S3C_CIPRSCCTRL_RGBFORMAT_24			(1 << 30)
+#define S3C_CIPRSCCTRL_RGBFORMAT_16			(0 << 30)
+
+#define S3C_CIPRSCCTRL_START				(1 << 15)
+
+#define S3C_CIPRSCCTRL_INRGB_FMT_PR_RGB888		(2 << 13)
+#define S3C_CIPRSCCTRL_INRGB_FMT_PR_RGB666		(1 << 13)
+#define S3C_CIPRSCCTRL_INRGB_FMT_PR_RGB565		(0 << 13)
+
+#define S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB888		(2 << 11)
+#define S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB666		(1 << 11)
+#define S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB565		(0 << 11)
+
+/* Preview Status Register */
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C_CIPRSTATUS_OVFICB_PR			(1 << 31)
+#define S3C_CIPRSTATUS_OVFICR_PR			(1 << 30)
+
+#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
+#define S3C_CIPRSTATUS_OVFIY_PR				(1 << 31)
+#define S3C_CIPRSTATUS_OVFICB_PR			(1 << 30)
+#define S3C_CIPRSTATUS_OVFICR_PR			(1 << 29)
+#endif
+
+/* Image Capture Enable Register */
+#define S3C_CIIMGCPT_IMGCPTEN				(1 << 31)
+#define S3C_CIIMGCPT_IMGCPTEN_COSC			(1 << 30)
+#define S3C_CIIMGCPT_IMGCPTEN_PRSC			(1 << 29)
+
+#define S3C_CIIMGCPT_CPT_CODMA_SEL_RGB			(1 << 26)
+#define S3C_CIIMGCPT_CPT_CODMA_SEL_YUV			(0 << 26)
+
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C_CIIMGCPT_CPT_CODMA_RGBFMT_24		(1 << 25)
+#define S3C_CIIMGCPT_CPT_CODMA_RGBFMT_16		(0 << 25)
+#define S3C_CIIMGCPT_CPT_CODMA_ENABLE			(1 << 24)
+#define S3C_CIIMGCPT_CPT_CODMA_DISABLE			(0 << 24)
+#define S3C_CIIMGCPT_CPT_CODMA_MOD_CNT			(1 << 18)
+#define S3C_CIIMGCPT_CPT_CODMA_MOD_EN			(0 << 18)
+
+#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
+#define S3C_CIIMGCPT_CPT_FREN_CO_ENABLE			(1 << 25)
+#define S3C_CIIMGCPT_CPT_FREN_CO_DISABLE		(0 << 25)
+#define S3C_CIIMGCPT_CPT_FREN_PR_ENABLE			(1 << 24)
+#define S3C_CIIMGCPT_CPT_FREN_PR_DISABLE		(0 << 24)
+#define S3C_CIIMGCPT_CPT_FRMOD_CNT			(1 << 18)
+#define S3C_CIIMGCPT_CPT_FRMOD_EN			(0 << 18)
+#endif
+
+/* Image Effects Register */
+#define S3C_CIIMGEFF_IE_ON_PR_ENABLE			(1 << 31)
+#define S3C_CIIMGEFF_IE_ON_PR_DISABLE			(0 << 31)
+
+#define S3C_CIIMGEFF_IE_ON_CO_ENABLE			(1 << 30)
+#define S3C_CIIMGEFF_IE_ON_CO_DISABLE			(0 << 30)
+
+#define S3C_CIIMGEFF_IE_AFTER_SC_BEFORE			(0 << 29)
+#define S3C_CIIMGEFF_IE_AFTER_SC_AFTER			(1 << 29)
+
+#define S3C_CIIMGEFF_FIN_SILHOUETTE			(5 << 26)
+#define S3C_CIIMGEFF_FIN_EMBOSSING			(4 << 26)
+#define S3C_CIIMGEFF_FIN_ARTFREEZE			(3 << 26)
+#define S3C_CIIMGEFF_FIN_NEGATIVE			(2 << 26)
+#define S3C_CIIMGEFF_FIN_ARBITRARY			(1 << 26)
+#define S3C_CIIMGEFF_FIN_BYPASS				(0 << 26)
+
+/* MSDMA for Codec Source Image Width Register */
+#define S3C_MSCOWIDTH_AUTOLOAD_ENABLE			(1 << 31)
+#define S3C_MSCOWIDTH_AUTOLOAD_DISABLE			(0 << 31)
+
+#define S3C_MSCOWIDTH_ADDR_CH_ENABLE			(1 << 30)
+#define S3C_MSCOWIDTH_ADDR_CH_DISABLE			(0 << 30)
+
+/* MSDMA Control Register */
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C_CIMSCTRL_INTERLEAVE_MS_INTERLEAVE		(1 << 5)
+#define S3C_CIMSCTRL_INTERLEAVE_MS_NONINTERLEAVE	(0 << 5)
+#define S3C_CIMSCTRL_ORDER422_MS_CRYCBY			(3 << 3)
+#define S3C_CIMSCTRL_ORDER422_MS_CBYCRY			(2 << 3)
+#define S3C_CIMSCTRL_ORDER422_MS_YCRYCB			(1 << 3)
+#define S3C_CIMSCTRL_ORDER422_MS_YCBYCR			(0 << 3)
+#define S3C_CIMSCTRL_SEL_DMA_CAM_MEMORY			(1 << 2)
+#define S3C_CIMSCTRL_SEL_DMA_CAM_EXTCAM			(0 << 2)
+#define S3C_CIMSCTRL_SRC420_MS_420			(1 << 1)
+#define S3C_CIMSCTRL_SRC420_MS_422			(0 << 1)
+#define S3C_CIMSCTRL_ENVID_MS_SET			(1 << 0)
+
+#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
+#define S3C_MSCOCTRL_BC_SEL_FRAME			(0 << 10)
+#define S3C_MSCOCTRL_BC_SEL_FIELD			(1 << 10)
+#define S3C_MSCOCTRL_BUFFER_INI_0			(0 << 8)
+#define S3C_MSCOCTRL_BUFFER_INI_1			(1 << 8)
+#define S3C_MSCOCTRL_TRG_MODE_SOFT			(0 << 7)
+#define S3C_MSCOCTRL_TRG_MODE_HARD			(1 << 7)
+#define S3C_MSCOCTRL_ORDER422_M_C_YCBYCR		(0 << 4)
+#define S3C_MSCOCTRL_ORDER422_M_C_YCRYCB		(1 << 4)
+#define S3C_MSCOCTRL_ORDER422_M_C_CBYCRY		(2 << 4)
+#define S3C_MSCOCTRL_ORDER422_M_C_CRYCBY		(3 << 4)
+#define S3C_MSCOCTRL_SEL_DMA_CAM_C_EXTCAM		(0 << 3)
+#define S3C_MSCOCTRL_SEL_DMA_CAM_C_MEMORY		(1 << 3)
+#define S3C_MSCOCTRL_INFORMAT_M_C_420			(0 << 1)
+#define S3C_MSCOCTRL_INFORMAT_M_C_422			(1 << 1)
+#define S3C_MSCOCTRL_INFORMAT_M_C_422_INT		(2 << 1)
+#define S3C_MSCOCTRL_INFORMAT_M_C_RGB			(3 << 1)
+#define S3C_MSCOCTRL_ENVID_M_C_SET			(1 << 0)
+#define S3C_MSPRCTRL_BC_SEL_FIELD			(0 << 10)
+#define S3C_MSPRCTRL_BC_SEL_FRAME			(1 << 10)
+#define S3C_MSPRCTRL_BUFFER_INI_0			(0 << 8)
+#define S3C_MSPRCTRL_BUFFER_INI_1			(1 << 8)
+#define S3C_MSPRCTRL_TRG_MODE_SOFT			(0 << 7)
+#define S3C_MSPRCTRL_TRG_MODE_HARD			(1 << 7)
+#define S3C_MSPRCTRL_ORDER422_M_P_YCBYCR		(0 << 4)
+#define S3C_MSPRCTRL_ORDER422_M_P_YCRYCB		(1 << 4)
+#define S3C_MSPRCTRL_ORDER422_M_P_CBYCRY		(2 << 4)
+#define S3C_MSPRCTRL_ORDER422_M_P_CRYCBY		(3 << 4)
+#define S3C_MSPRCTRL_SEL_DMA_CAM_P_EXTCAM		(0 << 3)
+#define S3C_MSPRCTRL_SEL_DMA_CAM_P_MEMORY		(1 << 3)
+#define S3C_MSPRCTRL_INFORMAT_M_P_420			(0 << 1)
+#define S3C_MSPRCTRL_INFORMAT_M_P_422			(1 << 1)
+#define S3C_MSPRCTRL_INFORMAT_M_P_422_INT		(2 << 1)
+#define S3C_MSPRCTRL_INFORMAT_M_P_RGB			(3 << 1)
+#define S3C_MSPRCTRL_ENVID_M_P_SET			(1 << 0)
+#endif
+
+/*************************************************************************
+ * Register part
+ ************************************************************************/
+#define S3C_CICOYSA(__x) 	S3C_CAMIFREG(0x18 + (__x) * 4)
+#define S3C_CICOCBSA(__x) 	S3C_CAMIFREG(0x28 + (__x) * 4)
+#define S3C_CICOCRSA(__x)  	S3C_CAMIFREG(0x38 + (__x) * 4)
+#define S3C_CIPRCLRSA(__x)  	S3C_CAMIFREG(0x6C + (__x) * 4)
+#define S3C_CIPRYSA(__x)     	S3C_CAMIFREG(0x6C + (__x) * 4)
+#define S3C_CIPRCBSA(__x)   	S3C_CAMIFREG(0x7C + (__x) * 4)
+#define S3C_CIPRCRSA(__x)   	S3C_CAMIFREG(0x8C + (__x) * 4)
+
+#define S3C_CISRCFMT		S3C_CAMIFREG(0x00)
+#define S3C_CIWDOFST		S3C_CAMIFREG(0x04)
+#define S3C_CIGCTRL		S3C_CAMIFREG(0x08)
+#define S3C_CIDOWSFT2		S3C_CAMIFREG(0x14)
+#define S3C_CICOYSA1		S3C_CAMIFREG(0x18)
+#define S3C_CICOYSA2		S3C_CAMIFREG(0x1C)
+#define S3C_CICOYSA3		S3C_CAMIFREG(0x20)
+#define S3C_CICOYSA4		S3C_CAMIFREG(0x24)
+#define S3C_CICOCBSA1		S3C_CAMIFREG(0x28)
+#define S3C_CICOCBSA2		S3C_CAMIFREG(0x2C)
+#define S3C_CICOCBSA3		S3C_CAMIFREG(0x30)
+#define S3C_CICOCBSA4		S3C_CAMIFREG(0x34)
+#define S3C_CICOCRSA1		S3C_CAMIFREG(0x38)
+#define S3C_CICOCRSA2		S3C_CAMIFREG(0x3C)
+#define S3C_CICOCRSA3		S3C_CAMIFREG(0x40)
+#define S3C_CICOCRSA4		S3C_CAMIFREG(0x44)
+#define S3C_CICOTRGFMT		S3C_CAMIFREG(0x48)	/* CODEC target format */
+#define S3C_CICOCTRL		S3C_CAMIFREG(0x4C)	/* CODEC DMA control register */
+#define S3C_CICOSCPRERATIO	S3C_CAMIFREG(0x50)	/* CODEC pre-scaler control register 1 */
+#define S3C_CICOSCPREDST	S3C_CAMIFREG(0x54)	/* CODEC pre-scaler control register 2 */
+#define S3C_CICOSCCTRL		S3C_CAMIFREG(0x58)	/* CODEC main-scaler control */
+#define S3C_CICOTAREA		S3C_CAMIFREG(0x5C)	/* CODEC DMA target area register */
+#define S3C_CICOSTATUS		S3C_CAMIFREG(0x64)	/* CODEC status register */
+
+#if defined (CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+#define S3C_CIPRCLRSA1		S3C_CAMIFREG(0x6C)	/* RGB 1st frame start address for preview DMA */
+#define S3C_CIPRCLRSA2		S3C_CAMIFREG(0x70)	/* RGB 2nd frame start address for preview DMA */
+#define S3C_CIPRCLRSA3		S3C_CAMIFREG(0x74)	/* RGB 3rd frame start address for preview DMA */
+#define S3C_CIPRCLRSA4		S3C_CAMIFREG(0x78)	/* RGB 4th frame start address for preview DMA */
+#define S3C_CIPRTRGFMT		S3C_CAMIFREG(0x7C)	/* PREVIEW target format register */
+#define S3C_CIPRCTRL		S3C_CAMIFREG(0x80)	/* PREVIEW DMA control register */
+#define S3C_CIPRSCPRERATIO	S3C_CAMIFREG(0x84)	/* PREVIEW pre-scaler control register 1 */
+#define S3C_CIPRSCPREDST	S3C_CAMIFREG(0x88)	/* PREVIEW pre-scaler control register 2 */
+#define S3C_CIPRSCCTRL		S3C_CAMIFREG(0x8C)	/* PREVIEW main-scaler control register */
+#define S3C_CIPRTAREA		S3C_CAMIFREG(0x90)	/* PREVIEW DMA target area register */
+#define S3C_CIPRSTATUS		S3C_CAMIFREG(0x98)	/* PREVIEW status register */
+#define S3C_CIIMGCPT		S3C_CAMIFREG(0xA0)	/* image capture enable register */
+#define S3C_CICOCPTSEQ		S3C_CAMIFREG(0xA4)	/* CODEC capture sequence register */
+#define S3C_CICOSCOS		S3C_CAMIFREG(0xA8)	/* CODEC scan line offset register */
+#define S3C_CIIMGEFF		S3C_CAMIFREG(0xB0)	/* image effect register */
+#define S3C_CIMSYSA		S3C_CAMIFREG(0xB4)	/* MSDMA Y start address register */
+#define S3C_CIMSCBSA		S3C_CAMIFREG(0xB8)	/* MSDMA CB start address register */
+#define S3C_CIMSCRSA		S3C_CAMIFREG(0xBC)	/* MSDMA CR start address register */
+#define S3C_CIMSYEND		S3C_CAMIFREG(0xC0)	/* MSDMA Y end address register */
+#define S3C_CIMSCBEND		S3C_CAMIFREG(0xC4)	/* MSDMA CB end address register */
+#define S3C_CIMSCREND		S3C_CAMIFREG(0xC8)	/* MSDMA CR end address register */
+#define S3C_CIMSYOFF		S3C_CAMIFREG(0xCC)	/* MSDMA Y offset register */
+#define S3C_CIMSCBOFF		S3C_CAMIFREG(0xD0)	/* MSDMA CB offset register */
+#define S3C_CIMSCROFF		S3C_CAMIFREG(0xD4)	/* MSDMA CR offset register */
+#define S3C_CIMSWIDTH		S3C_CAMIFREG(0xD8)	/* MSDMA source image width register */
+#define S3C_CIMSCTRL		S3C_CAMIFREG(0xDC)	/* MSDMA control register */
+
+#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
+#define S3C_CIPRYSA1		S3C_CAMIFREG(0x6C)	/* 1st frame start address for preview DMA */
+#define S3C_CIPRYSA2		S3C_CAMIFREG(0x70)	/* 2nd frame start address for preview DMA */
+#define S3C_CIPRYSA3		S3C_CAMIFREG(0x74)	/* 3rd frame start address for preview DMA */
+#define S3C_CIPRYSA4		S3C_CAMIFREG(0x78)	/* 4th frame start address for preview DMA */
+#define S3C_CIPRCBSA1		S3C_CAMIFREG(0x7C)	/* 1st frame start address for preview DMA */
+#define S3C_CIPRCBSA2		S3C_CAMIFREG(0x80)	/* 2nd frame start address for preview DMA */
+#define S3C_CIPRCBSA3		S3C_CAMIFREG(0x84)	/* 3rd frame start address for preview DMA */
+#define S3C_CIPRCBSA4		S3C_CAMIFREG(0x88)	/* 4th frame start address for preview DMA */
+#define S3C_CIPRCRSA1		S3C_CAMIFREG(0x8C)	/* 1st frame start address for preview DMA */
+#define S3C_CIPRCRSA2		S3C_CAMIFREG(0x90)	/* 2nd frame start address for preview DMA */
+#define S3C_CIPRCRSA3		S3C_CAMIFREG(0x94)	/* 3rd frame start address for preview DMA */
+#define S3C_CIPRCRSA4		S3C_CAMIFREG(0x98)	/* 4th frame start address for preview DMA */
+#define S3C_CIPRTRGFMT		S3C_CAMIFREG(0x9C)	/* PREVIEW target format register */
+#define S3C_CIPRCTRL		S3C_CAMIFREG(0xA0)	/* PREVIEW DMA control register */
+#define S3C_CIPRSCPRERATIO	S3C_CAMIFREG(0xA4)	/* PREVIEW pre-scaler control register 1 */
+#define S3C_CIPRSCPREDST	S3C_CAMIFREG(0xA8)	/* PREVIEW pre-scaler control register 2 */
+#define S3C_CIPRSCCTRL		S3C_CAMIFREG(0xAC)	/* PREVIEW main-scaler control register */
+#define S3C_CIPRTAREA		S3C_CAMIFREG(0xB0)	/* PREVIEW DMA target area register */
+#define S3C_CIPRSTATUS		S3C_CAMIFREG(0xB8)	/* PREVIEW status register */
+#define S3C_CIIMGCPT		S3C_CAMIFREG(0xC0)	/* image capture enable register */
+#define S3C_CICOCPTSEQ		S3C_CAMIFREG(0xC4)	/* CODEC capture sequence register */
+#define S3C_CIIMGEFF		S3C_CAMIFREG(0xD0)	/* image effect register */
+#define S3C_MSCOY0SA		S3C_CAMIFREG(0xD4)	/* MSDMA for CODEC Y start address register */
+#define S3C_MSCOCB0SA		S3C_CAMIFREG(0xD8)	/* MSDMA for CODEC CB start address register */
+#define S3C_MSCOCR0SA		S3C_CAMIFREG(0xDC)	/* MSDMA for CODEC CR start address register */
+#define S3C_MSCOY0END		S3C_CAMIFREG(0xE0)	/* MSDMA for CODEC Y end address register */
+#define S3C_MSCOCB0END		S3C_CAMIFREG(0xE4)	/* MSDMA for CODEC CB end address register */
+#define S3C_MSCOCR0END		S3C_CAMIFREG(0xE8)	/* MSDMA for CODEC CR end address register */
+#define S3C_MSCOYOFF		S3C_CAMIFREG(0xEC)	/* MSDMA for CODEC Y offset register */
+#define S3C_MSCOCBOFF		S3C_CAMIFREG(0xF0)	/* MSDMA for CODEC CB offset register */
+#define S3C_MSCOCROFF		S3C_CAMIFREG(0xF4)	/* MSDMA for CODEC CR offset register */
+#define S3C_MSCOWIDTH		S3C_CAMIFREG(0xF8)	/* MSDMA for CODEC source image width register */
+#define S3C_MSCOCTRL		S3C_CAMIFREG(0xFC)	/* MSDMA for CODEC control register */
+#define S3C_MSPRY0SA		S3C_CAMIFREG(0x100)	/* MSDMA for PREVIEW Y0 start address register */
+#define S3C_MSPRCB0SA		S3C_CAMIFREG(0x104)	/* MSDMA for PREVIEW CB0 start address register */
+#define S3C_MSPRCR0SA		S3C_CAMIFREG(0x108)	/* MSDMA for PREVIEW CR0 start address register */
+#define S3C_MSPRY0END		S3C_CAMIFREG(0x10C)	/* MSDMA for PREVIEW Y0 end address register */
+#define S3C_MSPRCB0END		S3C_CAMIFREG(0x110)	/* MSDMA for PREVIEW CB0 end address register */
+#define S3C_MSPRCR0END		S3C_CAMIFREG(0x114)	/* MSDMA for PREVIEW CR0 end address register */
+#define S3C_MSPRYOFF		S3C_CAMIFREG(0x118)	/* MSDMA for PREVIEW Y offset register */
+#define S3C_MSPRCBOFF		S3C_CAMIFREG(0x11C)	/* MSDMA for PREVIEW CB offset register */
+#define S3C_MSPRCROFF		S3C_CAMIFREG(0x120)	/* MSDMA for PREVIEW CR offset register */
+#define S3C_MSPRWIDTH		S3C_CAMIFREG(0x124)	/* MSDMA for PREVIEW source image width register */
+#define S3C_CIMSCTRL		S3C_CAMIFREG(0x128)	/* MSDMA for PREVIEW control register */
+#define S3C_CICOSCOSY		S3C_CAMIFREG(0x12C)	/* CODEC scan line Y offset register */
+#define S3C_CICOSCOSCB		S3C_CAMIFREG(0x130)	/* CODEC scan line CB offset register */
+#define S3C_CICOSCOSCR		S3C_CAMIFREG(0x134)	/* CODEC scan line CR offset register */
+#define S3C_CIPRSCOSY		S3C_CAMIFREG(0x138)	/* PREVIEW scan line Y offset register */
+#define S3C_CIPRSCOSCB		S3C_CAMIFREG(0x13C)	/* PREVIEW scan line CB offset register */
+#define S3C_CIPRSCOSCR		S3C_CAMIFREG(0x140)	/* PREVIEW scan line CR offset register */
+#endif
+
+#endif /* ___ASM_ARCH_REGS_CAMIF_H */
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-clock.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-clock.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-clock.h	2009-04-10 11:13:25.000000000 +0900
@@ -25,6 +25,7 @@
 #define S3C_EPLL_CON0		S3C_CLKREG(0x14)
 #define S3C_EPLL_CON1		S3C_CLKREG(0x18)
 #define S3C_CLK_SRC		S3C_CLKREG(0x1C)
+#define S3C_CLK_SRC2		S3C_CLKREG(0x10C)
 #define S3C_CLK_DIV0		S3C_CLKREG(0x20)
 #define S3C_CLK_DIV1		S3C_CLKREG(0x24)
 #define S3C_CLK_DIV2		S3C_CLKREG(0x28)
@@ -32,6 +33,7 @@
 #define S3C_HCLK_GATE		S3C_CLKREG(0x30)
 #define S3C_PCLK_GATE		S3C_CLKREG(0x34)
 #define S3C_SCLK_GATE		S3C_CLKREG(0x38)
+#define S3C_MEM0_GATE		S3C_CLKREG(0x3C)
 
 /* CLKDIV0 */
 #define S3C6400_CLKDIV0_MFC_MASK	(0xf << 28)
@@ -88,10 +90,10 @@
 
 /* HCLK GATE Registers */
 #define S3C_CLKCON_HCLK_BUS	(1<<30)
-#define S3C_CLKCON_HCLK_SECUR	(1<<29)
-#define S3C_CLKCON_HCLK_SDMA1	(1<<28)
-#define S3C_CLKCON_HCLK_SDMA2	(1<<27)
-#define S3C_CLKCON_HCLK_UHOST	(1<<26)
+#define S3C_CLKCON_HCLK_UHOST	(1<<29)
+#define S3C_CLKCON_HCLK_SECUR	(1<<28)
+#define S3C_CLKCON_HCLK_SDMA1	(1<<27)
+#define S3C_CLKCON_HCLK_SDMA0	(1<<26)
 #define S3C_CLKCON_HCLK_IROM	(1<<25)
 #define S3C_CLKCON_HCLK_DDR1	(1<<24)
 #define S3C_CLKCON_HCLK_DDR0	(1<<23)
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO memory port register definitions
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
+#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
+
+#define S3C64XX_MEM0CONSTOP	S3C64XX_GPIOREG(0x1B0)
+#define S3C64XX_MEM1CONSTOP	S3C64XX_GPIOREG(0x1B4)
+
+#define S3C64XX_MEM0CONSLP0	S3C64XX_GPIOREG(0x1C0)
+#define S3C64XX_MEM0CONSLP1	S3C64XX_GPIOREG(0x1C4)
+#define S3C64XX_MEM1CONSLP	S3C64XX_GPIOREG(0x1C8)
+
+#define S3C64XX_MEM0DRVCON	S3C64XX_GPIOREG(0x1D0)
+#define S3C64XX_MEM1DRVCON	S3C64XX_GPIOREG(0x1D4)
+
+#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h	2009-04-10 11:13:25.000000000 +0900
@@ -13,23 +13,176 @@
 
 /* Base addresses for each of the banks */
 
-#define S3C64XX_GPA_BASE	(S3C64XX_VA_GPIO + 0x0000)
-#define S3C64XX_GPB_BASE	(S3C64XX_VA_GPIO + 0x0020)
-#define S3C64XX_GPC_BASE	(S3C64XX_VA_GPIO + 0x0040)
-#define S3C64XX_GPD_BASE	(S3C64XX_VA_GPIO + 0x0060)
-#define S3C64XX_GPE_BASE	(S3C64XX_VA_GPIO + 0x0080)
-#define S3C64XX_GPF_BASE	(S3C64XX_VA_GPIO + 0x00A0)
-#define S3C64XX_GPG_BASE	(S3C64XX_VA_GPIO + 0x00C0)
-#define S3C64XX_GPH_BASE	(S3C64XX_VA_GPIO + 0x00E0)
-#define S3C64XX_GPI_BASE	(S3C64XX_VA_GPIO + 0x0100)
-#define S3C64XX_GPJ_BASE	(S3C64XX_VA_GPIO + 0x0120)
-#define S3C64XX_GPK_BASE	(S3C64XX_VA_GPIO + 0x0800)
-#define S3C64XX_GPL_BASE	(S3C64XX_VA_GPIO + 0x0810)
-#define S3C64XX_GPM_BASE	(S3C64XX_VA_GPIO + 0x0820)
-#define S3C64XX_GPN_BASE	(S3C64XX_VA_GPIO + 0x0830)
-#define S3C64XX_GPO_BASE	(S3C64XX_VA_GPIO + 0x0140)
-#define S3C64XX_GPP_BASE	(S3C64XX_VA_GPIO + 0x0160)
-#define S3C64XX_GPQ_BASE	(S3C64XX_VA_GPIO + 0x0180)
+#define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))
+
+#define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
+#define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
+#define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
+#define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
+#define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
+#define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
+#define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
+#define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
+#define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
+#define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
+#define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
+#define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
+#define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
+#define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
+#define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
+#define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
+#define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)
+#define S3C64XX_SPC_BASE	S3C64XX_GPIOREG(0x01A0)
+
+/* SPCON */
+
+#define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)
+
+#define S3C64XX_SPCON_DRVCON_CAM_MASK		(0x3 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_SHIFT		(30)
+#define S3C64XX_SPCON_DRVCON_CAM_2mA		(0x0 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_4mA		(0x1 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_7mA		(0x2 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_9mA		(0x3 << 30)
+
+#define S3C64XX_SPCON_DRVCON_HSSPI_MASK		(0x3 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT	(28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_2mA		(0x0 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_4mA		(0x1 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_7mA		(0x2 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_9mA		(0x3 << 28)
+
+#define S3C64XX_SPCON_DRVCON_HSMMC_MASK		(0x3 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT	(26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_2mA		(0x0 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_4mA		(0x1 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_7mA		(0x2 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_9mA		(0x3 << 26)
+
+#define S3C64XX_SPCON_DRVCON_LCD_MASK		(0x3 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_SHIFT		(24)
+#define S3C64XX_SPCON_DRVCON_LCD_2mA		(0x0 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_4mA		(0x1 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_7mA		(0x2 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_9mA		(0x3 << 24)
+
+#define S3C64XX_SPCON_DRVCON_MODEM_MASK		(0x3 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT	(22)
+#define S3C64XX_SPCON_DRVCON_MODEM_2mA		(0x0 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_4mA		(0x1 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_7mA		(0x2 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_9mA		(0x3 << 22)
+
+#define S3C64XX_SPCON_nRSTOUT_OEN		(1 << 21)
+
+#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK	(0x3 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT	(18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA	(0x0 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA	(0x1 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA	(0x2 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA	(0x3 << 18)
+
+#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK		(0x3 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT	(16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED	(0x0 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN		(0x1 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_UP		(0x2 << 16)
+
+#define S3C64XX_SPCON_MEM1_D_PUD1_MASK		(0x3 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT		(14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED	(0x0 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN		(0x1 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_UP		(0x2 << 14)
+
+#define S3C64XX_SPCON_MEM1_D_PUD0_MASK		(0x3 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT		(12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED	(0x0 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN		(0x1 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_UP		(0x2 << 12)
+
+#define S3C64XX_SPCON_MEM0_D_PUD_MASK		(0x3 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT		(8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED	(0x0 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DOWN		(0x1 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_UP		(0x2 << 8)
+
+#define S3C64XX_SPCON_USBH_DMPD			(1 << 7)
+#define S3C64XX_SPCON_USBH_DPPD			(1 << 6)
+#define S3C64XX_SPCON_USBH_PUSW2		(1 << 5)
+#define S3C64XX_SPCON_USBH_PUSW1		(1 << 4)
+#define S3C64XX_SPCON_USBH_SUSPND		(1 << 3)
+
+#define S3C64XX_SPCON_LCD_SEL_MASK		(0x3 << 0)
+#define S3C64XX_SPCON_LCD_SEL_SHIFT		(0)
+#define S3C64XX_SPCON_LCD_SEL_HOST		(0x0 << 0)
+#define S3C64XX_SPCON_LCD_SEL_RGB		(0x1 << 0)
+#define S3C64XX_SPCON_LCD_SEL_606_656		(0x2 << 0)
+
+
+/* External interrupt registers */
+
+#define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)
+#define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)
+#define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)
+#define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)
+#define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)
+
+#define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)
+#define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)
+#define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)
+#define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)
+#define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)
+
+#define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)
+#define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)
+#define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)
+#define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)
+#define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)
+
+#define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)
+#define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)
+#define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)
+#define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)
+#define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)
+
+#define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)
+#define S3C64XX_PRIORITY_ARB(x)	(1 << (x))
+
+#define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)
+#define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)
+
+#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
+#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
+#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
+#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
+#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
+#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)
+
+#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
+#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)
+
+/* GPIO sleep configuration */
+
+#define S3C64XX_SPCONSLP	S3C64XX_GPIOREG(0x880)
+
+#define S3C64XX_SPCONSLP_TDO_PULLDOWN	(1 << 14)
+#define S3C64XX_SPCONSLP_CKE1INIT	(1 << 5)
+
+#define S3C64XX_SPCONSLP_RSTOUT_MASK	(0x3 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT0	(0x0 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT1	(0x1 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_HIZ	(0x2 << 12)
+
+#define S3C64XX_SPCONSLP_KPCOL_MASK	(0x3 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT0	(0x0 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT1	(0x1 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_INP	(0x2 << 0)
+
+
+#define S3C64XX_SLPEN		S3C64XX_GPIOREG(0x930)
+
+#define S3C64XX_SLPEN_USE_xSLP		(1 << 0)
+#define S3C64XX_SLPEN_CFG_BYSLPEN	(1 << 1)
 
 #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-modem.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-modem.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-modem.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,31 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - modem block registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_MODEM_H
+#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
+
+#define S3C64XX_MODEMREG(x)	(S3C64XX_VA_MODEM + (x))
+
+#define S3C64XX_MODEM_INT2AP			S3C64XX_MODEMREG(0x0)
+#define S3C64XX_MODEM_INT2MODEM			S3C64XX_MODEMREG(0x4)
+#define S3C64XX_MODEM_MIFCON			S3C64XX_MODEMREG(0x8)
+#define S3C64XX_MODEM_MIFPCON			S3C64XX_MODEMREG(0xC)
+#define S3C64XX_MODEM_INTCLR			S3C64XX_MODEMREG(0x10)
+#define S3C64XX_MODEM_DMA_TXADDR		S3C64XX_MODEMREG(0x14)
+#define S3C64XX_MODEM_DMA_RXADDR		S3C64XX_MODEMREG(0x18)
+
+#define MIFPCON_INT2M_LEVEL			(1 << 4)
+#define MIFPCON_LCD_BYPASS			(1 << 3)
+
+#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-sys.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-sys.h	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-sys.h	2009-04-10 11:13:25.000000000 +0900
@@ -17,6 +17,10 @@
 
 #define S3C_SYSREG(x)		(S3C_VA_SYS + (x))
 
+#define S3C64XX_AHB_CON0	S3C_SYSREG(0x100)
+#define S3C64XX_AHB_CON1	S3C_SYSREG(0x104)
+#define S3C64XX_AHB_CON2	S3C_SYSREG(0x108)
+
 #define S3C64XX_OTHERS		S3C_SYSREG(0x900)
 
 #define S3C64XX_OTHERS_USBMASK	(1 << 16)
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,116 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - syscon power and sleep control registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
+#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
+
+#define S3C64XX_PWR_CFG				S3C_SYSREG(0x804)
+
+#define S3C64XX_PWRCFG_OSC_OTG_DISABLE		(1 << 17)
+#define S3C64XX_PWRCFG_MMC2_DISABLE		(1 << 16)
+#define S3C64XX_PWRCFG_MMC1_DISABLE		(1 << 15)
+#define S3C64XX_PWRCFG_MMC0_DISABLE		(1 << 14)
+#define S3C64XX_PWRCFG_HSI_DISABLE		(1 << 13)
+#define S3C64XX_PWRCFG_TS_DISABLE		(1 << 12)
+#define S3C64XX_PWRCFG_RTC_TICK_DISABLE		(1 << 11)
+#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE	(1 << 10)
+#define S3C64XX_PWRCFG_MSM_DISABLE		(1 << 9)
+#define S3C64XX_PWRCFG_KEY_DISABLE		(1 << 8)
+#define S3C64XX_PWRCFG_BATF_DISABLE		(1 << 7)
+
+#define S3C64XX_PWRCFG_CFG_WFI_MASK		(0x3 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SHIFT		(5)
+#define S3C64XX_PWRCFG_CFG_WFI_IGNORE		(0x0 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_IDLE		(0x1 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_STOP		(0x2 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SLEEP		(0x3 << 5)
+
+#define S3C64XX_PWRCFG_CFG_BATFLT_MASK		(0x3 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT		(3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE	(0x0 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ		(0x1 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP		(0x3 << 3)
+
+#define S3C64XX_PWRCFG_CFG_BAT_WAKE		(1 << 2)
+#define S3C64XX_PWRCFG_OSC27_EN			(1 << 0)
+
+#define S3C64XX_EINT_MASK			S3C_SYSREG(0x808)
+
+#define S3C64XX_NORMAL_CFG			S3C_SYSREG(0x810)
+
+#define S3C64XX_NORMALCFG_IROM_ON		(1 << 30)
+#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON		(1 << 16)
+#define S3C64XX_NORMALCFG_DOMAIN_S_ON		(1 << 15)
+#define S3C64XX_NORMALCFG_DOMAIN_F_ON		(1 << 14)
+#define S3C64XX_NORMALCFG_DOMAIN_P_ON		(1 << 13)
+#define S3C64XX_NORMALCFG_DOMAIN_I_ON		(1 << 12)
+#define S3C64XX_NORMALCFG_DOMAIN_G_ON		(1 << 10)
+#define S3C64XX_NORMALCFG_DOMAIN_V_ON		(1 << 9)
+
+#define S3C64XX_STOP_CFG			S3C_SYSREG(0x814)
+
+#define S3C64XX_STOPCFG_MEMORY_ARM_ON		(1 << 29)
+#define S3C64XX_STOPCFG_TOP_MEMORY_ON		(1 << 20)
+#define S3C64XX_STOPCFG_ARM_LOGIC_ON		(1 << 17)
+#define S3C64XX_STOPCFG_TOP_LOGIC_ON		(1 << 8)
+#define S3C64XX_STOPCFG_OSC_EN			(1 << 0)
+
+#define S3C64XX_SLEEP_CFG			S3C_SYSREG(0x818)
+
+#define S3C64XX_SLEEPCFG_OSC_EN			(1 << 0)
+
+#define S3C64XX_STOP_MEM_CFG			S3C_SYSREG(0x81c)
+
+#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN	(1 << 6)
+#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN	(1 << 5)
+#define S3C64XX_STOPMEMCFG_OTG_RETAIN		(1 << 4)
+#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN		(1 << 3)
+#define S3C64XX_STOPMEMCFG_IROM_RETAIN		(1 << 2)
+#define S3C64XX_STOPMEMCFG_IRDA_RETAIN		(1 << 1)
+#define S3C64XX_STOPMEMCFG_NFCON_RETAIN		(1 << 0)
+
+#define S3C64XX_OSC_STABLE			S3C_SYSREG(0x824)
+#define S3C64XX_PWR_STABLE			S3C_SYSREG(0x828)
+
+#define S3C64XX_WAKEUP_STAT			S3C_SYSREG(0x908)
+
+#define S3C64XX_WAKEUPSTAT_MMC2			(1 << 11)
+#define S3C64XX_WAKEUPSTAT_MMC1			(1 << 10)
+#define S3C64XX_WAKEUPSTAT_MMC0			(1 << 9)
+#define S3C64XX_WAKEUPSTAT_HSI			(1 << 8)
+#define S3C64XX_WAKEUPSTAT_BATFLT		(1 << 6)
+#define S3C64XX_WAKEUPSTAT_MSM			(1 << 5)
+#define S3C64XX_WAKEUPSTAT_KEY			(1 << 4)
+#define S3C64XX_WAKEUPSTAT_TS			(1 << 3)
+#define S3C64XX_WAKEUPSTAT_RTC_TICK		(1 << 2)
+#define S3C64XX_WAKEUPSTAT_RTC_ALARM		(1 << 1)
+#define S3C64XX_WAKEUPSTAT_EINT			(1 << 0)
+
+#define S3C64XX_BLK_PWR_STAT			S3C_SYSREG(0x90c)
+
+#define S3C64XX_BLKPWRSTAT_G			(1 << 7)
+#define S3C64XX_BLKPWRSTAT_ETM			(1 << 6)
+#define S3C64XX_BLKPWRSTAT_S			(1 << 5)
+#define S3C64XX_BLKPWRSTAT_F			(1 << 4)
+#define S3C64XX_BLKPWRSTAT_P			(1 << 3)
+#define S3C64XX_BLKPWRSTAT_I			(1 << 2)
+#define S3C64XX_BLKPWRSTAT_V			(1 << 1)
+#define S3C64XX_BLKPWRSTAT_TOP			(1 << 0)
+
+#define S3C64XX_INFORM0				S3C_SYSREG(0xA00)
+#define S3C64XX_INFORM1				S3C_SYSREG(0xA04)
+#define S3C64XX_INFORM2				S3C_SYSREG(0xA08)
+#define S3C64XX_INFORM3				S3C_SYSREG(0xA0C)
+
+#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/tzic-sp890.h android_2.6.29/arch/arm/plat-s3c64xx/include/plat/tzic-sp890.h
--- android_2.6.29_org/arch/arm/plat-s3c64xx/include/plat/tzic-sp890.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/include/plat/tzic-sp890.h	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,21 @@
+#ifndef __S3C64XX_TZIC_SP890_H__
+#define __S3C64XX_TZIC_SP890_H__
+
+
+#define S3C64XX_VA_TZIC0_FIQ_STATUS (S3C_VA_TZIC0 + SP890_TZIC_FIQSTATUS)
+#define S3C64XX_VA_TZIC0_RAWINTR (S3C_VA_TZIC0 + SP890_TZIC_RAWINTR)
+#define S3C64XX_VA_TZIC0_INTSELECT (S3C_VA_TZIC0 + SP890_TZIC_INTSELECT)
+#define S3C64XX_VA_TZIC0_FIQENABLE (S3C_VA_TZIC0 + SP890_TZIC_FIQENABLE)
+#define S3C64XX_VA_TZIC0_FIQENCLEAR (S3C_VA_TZIC0 + SP890_TZIC_FIQENCLEAR)
+#define S3C64XX_VA_TZIC0_FIQBYPASS (S3C_VA_TZIC0 + SP890_TZIC_FIQBYPASS)
+#define S3C64XX_VA_TZIC0_FPROTECTION (S3C_VA_TZIC0 + SP890_TZIC_PROTECTION)
+#define S3C64XX_VA_TZIC0_LOCK (S3C_VA_TZIC0 + SP890_TZIC_LOCK)
+#define S3C64XX_VA_TZIC0_LOCKSTATUS (S3C_VA_TZIC0 + SP890_TZIC_LOCKSTATUS)
+#define S3C64XX_VA_TZIC0_ITCR (S3C_VA_TZIC0 + SP890_TZIC_ITCR)
+#define S3C64XX_VA_TZIC0_ITIP1 (S3C_VA_TZIC0 + SP890_TZIC_ITIP1)
+#define S3C64XX_VA_TZIC0_ITIP2 (S3C_VA_TZIC0 + SP890_TZIC_ITIP2)
+#define S3C64XX_VA_TZIC0_ITOP1 (S3C_VA_TZIC0 + SP890_TZIC_ITOP1)
+#define S3C64XX_VA_TZIC0_ITOP2 (S3C_VA_TZIC0 + SP890_TZIC_ITOP2)
+#define S3C64XX_VA_TZIC0_PERIPHIDO (S3C_VA_TZIC0 + SP890_TZIC_PERIPHIDO)
+
+#endif
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/irq-eint.c android_2.6.29/arch/arm/plat-s3c64xx/irq-eint.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/irq-eint.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/irq-eint.c	2009-04-17 13:04:39.000000000 +0900
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 
 #include <asm/hardware/vic.h>
 
@@ -26,20 +27,7 @@
 
 #include <mach/map.h>
 #include <plat/cpu.h>
-
-/* GPIO is 0x7F008xxx, */
-#define S3C64XX_GPIOREG(x)	(S3C64XX_VA_GPIO + (x))
-
-#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
-#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
-#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
-#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
-#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
-#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)
-
-#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
-#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)
-
+#include <plat/pm.h>
 
 #define eint_offset(irq)	((irq) - IRQ_EINT(0))
 #define eint_irq_to_bit(irq)	(1 << eint_offset(irq))
@@ -91,6 +79,9 @@
 	else
 		reg = S3C64XX_EINT0CON1;
 
+	//if(irq == 11)
+	//  type = IRQ_TYPE_LEVEL_HIGH;
+
 	switch (type) {
 	case IRQ_TYPE_NONE:
 		printk(KERN_WARNING "No edge setting!\n");
@@ -137,7 +128,6 @@
 		pin = S3C64XX_GPM(offs - 23);
 
 	s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
-
 	return 0;
 }
 
@@ -148,6 +138,7 @@
 	.mask_ack	= s3c_irq_eint_maskack,
 	.ack		= s3c_irq_eint_ack,
 	.set_type	= s3c_irq_eint_set_type,
+	.set_wake	= s3c_irqext_wake,
 };
 
 /* s3c_irq_demux_eint
@@ -194,7 +185,7 @@
 	s3c_irq_demux_eint(20, 27);
 }
 
-static int __init s3c64xx_init_irq_eint(void)
+int __init s3c64xx_init_irq_eint(void)
 {
 	int irq;
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/irq-pm.c android_2.6.29/arch/arm/plat-s3c64xx/irq-pm.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/irq-pm.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/irq-pm.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,173 @@
+/* arch/arm/plat-s3c64xx/irq-pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Interrupt handling Power Management
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/serial_core.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/vic.h>
+
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-timer.h>
+#include <plat/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+/* We handled all the IRQ types in this code, to save having to make several
+ * small files to handle each different type separately. Having the EINT_GRP
+ * code here shouldn't be as much bloat as the IRQ table space needed when
+ * they are enabled. The added benefit is we ensure that these registers are
+ * in the same state as we suspended.
+ */
+
+static struct sleep_save irq_save[] = {
+	SAVE_ITEM(S3C64XX_PRIORITY),
+	SAVE_ITEM(S3C64XX_EINT0CON0),
+	SAVE_ITEM(S3C64XX_EINT0CON1),
+	SAVE_ITEM(S3C64XX_EINT0FLTCON0),
+	SAVE_ITEM(S3C64XX_EINT0FLTCON1),
+	SAVE_ITEM(S3C64XX_EINT0FLTCON2),
+	SAVE_ITEM(S3C64XX_EINT0FLTCON3),
+	SAVE_ITEM(S3C64XX_EINT0MASK),
+	SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+
+static struct irq_grp_save {
+	u32	fltcon;
+	u32	con;
+	u32	mask;
+} eint_grp_save[5];
+
+struct irq_vic_save {
+	u32	int_select;
+	u32	int_enable;
+	u32	soft_int;
+	u32	protect;
+	u32	vect_addr[32];
+	u32	vect_cntl[32];
+};
+
+static struct irq_vic_save irq_pm_vic0_save;
+static struct irq_vic_save irq_pm_vic1_save;
+
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save)
+{
+	int v;
+
+	save->int_select = readl(base + VIC_INT_SELECT);
+	save->int_enable = readl(base + VIC_INT_ENABLE);
+	save->soft_int = readl(base + VIC_INT_SOFT);
+	save->protect = readl(base + VIC_PROTECT);
+
+	S3C_PMDBG("%s: select=%08x, enable=%08x, protect=%08x\n", __func__,
+		  save->int_select, save->int_enable, save->protect);
+
+	for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
+		save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4));
+		save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4));
+	}
+}
+
+static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save)
+{
+	int v;
+
+	writel(save->int_select, base + VIC_INT_SELECT);
+	writel(save->protect, base + VIC_PROTECT);
+
+	/* set the enabled ints and then clear the non-enabled */
+	writel(save->int_enable, base + VIC_INT_ENABLE);
+	writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR);
+
+	/* and the same for the soft-int register */
+
+	writel(save->soft_int, base + VIC_INT_SOFT);
+	writel(~save->soft_int, base + VIC_INT_SOFT_CLEAR);
+
+	S3C_PMDBG("%s: vic int_enable=%08x\n", __func__, readl(base + VIC_INT_ENABLE));
+
+	for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
+		writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4));
+		writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4));
+	}
+}
+
+static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+	struct irq_grp_save *grp = eint_grp_save;
+	int i;
+
+	S3C_PMDBG("%s: suspending IRQs\n", __func__);
+
+	s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save);
+	s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save);
+
+	s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+	for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+		irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+	for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+		grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
+		grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
+		grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
+	}
+
+	return 0;
+}
+
+static int s3c64xx_irq_pm_resume(struct sys_device *dev)
+{
+	struct irq_grp_save *grp = eint_grp_save;
+	int i;
+
+	S3C_PMDBG("%s: resuming IRQs\n", __func__);
+
+	s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+
+	s3c64xx_vic_restore(S3C_VA_VIC0, &irq_pm_vic0_save);
+	s3c64xx_vic_restore(S3C_VA_VIC1, &irq_pm_vic1_save);
+
+	for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+		__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+	for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+		__raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
+		__raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
+		__raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
+	}
+
+	S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+	return 0;
+}
+
+static struct sysdev_driver s3c64xx_irq_driver = {
+	.suspend = s3c64xx_irq_pm_suspend,
+	.resume	 = s3c64xx_irq_pm_resume,
+};
+
+static int __init s3c64xx_irq_pm_init(void)
+{
+	return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
+}
+
+arch_initcall(s3c64xx_irq_pm_init);
+
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/irq.c android_2.6.29/arch/arm/plat-s3c64xx/irq.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/irq.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/irq.c	2009-04-10 11:13:25.000000000 +0900
@@ -14,12 +14,14 @@
 
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
+#include <linux/serial_core.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 
 #include <asm/hardware/vic.h>
 
 #include <mach/map.h>
+#include <plat/regs-serial.h>
 #include <plat/regs-timer.h>
 #include <plat/cpu.h>
 
@@ -135,9 +137,6 @@
 }
 
 /* UART interrupt registers, not worth adding to seperate include header */
-#define S3C64XX_UINTP	0x30
-#define S3C64XX_UINTSP	0x34
-#define S3C64XX_UINTM	0x38
 
 static void s3c_irq_uart_mask(unsigned int irq)
 {
@@ -207,7 +206,7 @@
 
 static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
 {
-	void __iomem *reg_base = uirq->regs;
+	void *reg_base = uirq->regs;
 	unsigned int irq;
 	int offs;
 
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/pm.c android_2.6.29/arch/arm/plat-s3c64xx/pm.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/pm.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/pm.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,177 @@
+/* linux/arch/arm/plat-s3c64xx/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU PM support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+
+#include <plat/pm.h>
+#include <plat/regs-sys.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-clock.h>
+#include <plat/regs-modem.h>
+#include <plat/regs-syscon-power.h>
+#include <plat/regs-gpio-memport.h>
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+#include <plat/gpio-bank-n.h>
+
+void s3c_pm_debug_smdkled(u32 set, u32 clear)
+{
+	unsigned long flags;
+	u32 reg;
+
+	local_irq_save(flags);
+	reg = __raw_readl(S3C64XX_GPNCON);
+	reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
+		 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
+	reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
+	       S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
+	__raw_writel(reg, S3C64XX_GPNCON);
+
+	reg = __raw_readl(S3C64XX_GPNDAT);
+	reg &= ~(clear << 12);
+	reg |= set << 12;
+	__raw_writel(reg, S3C64XX_GPNDAT);
+
+	local_irq_restore(flags);
+}
+#endif
+
+static struct sleep_save core_save[] = {
+	SAVE_ITEM(S3C_APLL_LOCK),
+	SAVE_ITEM(S3C_MPLL_LOCK),
+	SAVE_ITEM(S3C_EPLL_LOCK),
+	SAVE_ITEM(S3C_CLK_SRC),
+	SAVE_ITEM(S3C_CLK_DIV0),
+	SAVE_ITEM(S3C_CLK_DIV1),
+	SAVE_ITEM(S3C_CLK_DIV2),
+	SAVE_ITEM(S3C_CLK_OUT),
+	SAVE_ITEM(S3C_HCLK_GATE),
+	SAVE_ITEM(S3C_PCLK_GATE),
+	SAVE_ITEM(S3C_SCLK_GATE),
+	SAVE_ITEM(S3C_MEM0_GATE),
+
+	SAVE_ITEM(S3C_EPLL_CON1),
+	SAVE_ITEM(S3C_EPLL_CON0),
+
+	SAVE_ITEM(S3C64XX_MEM0DRVCON),
+	SAVE_ITEM(S3C64XX_MEM1DRVCON),
+
+#ifndef CONFIG_CPU_FREQ
+	SAVE_ITEM(S3C_APLL_CON),
+	SAVE_ITEM(S3C_MPLL_CON),
+#endif
+};
+
+static struct sleep_save misc_save[] = {
+	SAVE_ITEM(S3C64XX_AHB_CON0),
+	SAVE_ITEM(S3C64XX_AHB_CON1),
+	SAVE_ITEM(S3C64XX_AHB_CON2),
+	
+	SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
+	SAVE_ITEM(S3C64XX_SPCON),
+
+	SAVE_ITEM(S3C64XX_MEM0CONSTOP),
+	SAVE_ITEM(S3C64XX_MEM1CONSTOP),
+	SAVE_ITEM(S3C64XX_MEM0CONSLP0),
+	SAVE_ITEM(S3C64XX_MEM0CONSLP1),
+	SAVE_ITEM(S3C64XX_MEM1CONSLP),
+};
+
+void s3c_pm_configure_extint(void)
+{
+	__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
+}
+
+void s3c_pm_restore_core(void)
+{
+	__raw_writel(0, S3C64XX_EINT_MASK);
+
+	s3c_pm_debug_smdkled(1 << 2, 0);
+
+	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
+	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
+}
+
+void s3c_pm_save_core(void)
+{
+	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
+	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
+}
+
+/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
+ * put the per-cpu code in here until any new cpu comes along and changes
+ * this.
+ */
+
+#include <plat/regs-gpio.h>
+
+static void s3c64xx_cpu_suspend(void)
+{
+	unsigned long tmp;
+
+	/* set our standby method to sleep */
+
+	tmp = __raw_readl(S3C64XX_PWR_CFG);
+	tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+	tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
+	__raw_writel(tmp, S3C64XX_PWR_CFG);
+
+	/* clear any old wakeup */
+
+	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
+		     S3C64XX_WAKEUP_STAT);
+
+	/* set the LED state to 0110 over sleep */
+	s3c_pm_debug_smdkled(3 << 1, 0xf);
+
+	/* issue the standby signal into the pm unit. Note, we
+	 * issue a write-buffer drain just in case */
+
+	tmp = 0;
+
+	asm("b 1f\n\t"
+	    ".align 5\n\t"
+	    "1:\n\t"
+	    "mcr p15, 0, %0, c7, c10, 5\n\t"
+	    "mcr p15, 0, %0, c7, c10, 4\n\t"
+	    "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
+
+	/* we should never get past here */
+
+	panic("sleep resumed to originator?");
+}
+
+static void s3c64xx_pm_prepare(void)
+{
+	/* store address of resume. */
+	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
+
+	/* ensure previous wakeup state is cleared before sleeping */
+	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
+}
+
+static int s3c64xx_pm_init(void)
+{
+	pm_cpu_prep = s3c64xx_pm_prepare;
+	pm_cpu_sleep = s3c64xx_cpu_suspend;
+	pm_uart_udivslot = 1;
+	return 0;
+}
+
+arch_initcall(s3c64xx_pm_init);
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/s3c6400-clock.c android_2.6.29/arch/arm/plat-s3c64xx/s3c6400-clock.c
--- android_2.6.29_org/arch/arm/plat-s3c64xx/s3c6400-clock.c	2009-04-20 13:34:51.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/s3c6400-clock.c	2009-04-10 11:13:25.000000000 +0900
@@ -24,6 +24,7 @@
 
 #include <mach/hardware.h>
 #include <mach/map.h>
+#include <mach/cpu.h>
 
 #include <plat/cpu-freq.h>
 
@@ -36,7 +37,7 @@
  * ext_xtal_mux for want of an actual name from the manual.
 */
 
-static struct clk clk_ext_xtal_mux = {
+struct clk clk_ext_xtal_mux = {
 	.name		= "ext_xtal",
 	.id		= -1,
 };
@@ -63,7 +64,7 @@
 	void __iomem		*reg_divider;
 };
 
-static struct clk clk_fout_apll = {
+struct clk clk_fout_apll = {
 	.name		= "fout_apll",
 	.id		= -1,
 };
@@ -78,7 +79,7 @@
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
-static struct clksrc_clk clk_mout_apll = {
+struct clksrc_clk clk_mout_apll = {
 	.clk	= {
 		.name		= "mout_apll",
 		.id		= -1,
@@ -88,7 +89,81 @@
 	.sources	= &clk_src_apll,
 };
 
-static struct clk clk_fout_epll = {
+static u32 clk_arm_div_mask(void)
+{
+	if (cpu_is_s3c6400())
+		return S3C6400_CLKDIV0_ARM_MASK;
+
+	if (cpu_is_s3c6410())
+		return S3C6410_CLKDIV0_ARM_MASK;
+
+	return 0;
+}
+
+static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	u32 val;
+
+	val = __raw_readl(S3C_CLK_DIV0);
+	val &= clk_arm_div_mask();
+
+	return rate / (val + 1);
+}
+
+static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	unsigned long parent = clk_get_rate(clk->parent);
+	int div;
+	int max = clk_arm_div_mask() + 1;
+
+	if (parent < rate)
+		return parent;
+
+	div = parent / rate;
+
+	if (div < 1)
+		div = 1;
+	if (div > max)
+		div = max;
+
+	return parent / div;
+}
+
+static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int div;
+	u32 val;
+	unsigned long flags;
+
+	div = (clk_get_rate(clk->parent) / rate) - 1;
+
+	if (div > clk_arm_div_mask())
+		return -EINVAL;
+
+	local_irq_save(flags);
+
+	val = __raw_readl(S3C_CLK_DIV0);
+	val &= ~clk_arm_div_mask();
+	val |= div;
+
+	__raw_writel(val, S3C_CLK_DIV0);
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static struct clk clk_arm = {
+	.name		= "armclk",
+	.id		= -1,
+	.parent		= &clk_mout_apll.clk,
+	.round_rate	= &s3c64xx_clk_arm_round_rate,
+	.get_rate	= s3c64xx_clk_arm_get_rate,
+	.set_rate	= s3c64xx_clk_arm_set_rate,
+};
+
+struct clk clk_fout_epll = {
 	.name		= "fout_epll",
 	.id		= -1,
 };
@@ -103,7 +178,7 @@
 	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),
 };
 
-static struct clksrc_clk clk_mout_epll = {
+struct clksrc_clk clk_mout_epll = {
 	.clk	= {
 		.name		= "mout_epll",
 		.id		= -1,
@@ -123,7 +198,7 @@
 	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
 };
 
-static struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk clk_mout_mpll = {
 	.clk = {
 		.name		= "mout_mpll",
 		.id		= -1,
@@ -145,7 +220,7 @@
 	return rate;
 }
 
-static struct clk clk_dout_mpll = {
+struct clk clk_dout_mpll = {
 	.name		= "dout_mpll",
 	.id		= -1,
 	.parent		= &clk_mout_mpll.clk,
@@ -189,10 +264,10 @@
 };
 
 static struct clk *clkset_uhost_list[] = {
-	&clk_48m,
 	&clk_mout_epll.clk,
 	&clk_dout_mpll,
 	&clk_fin_epll,
+	&clk_48m,
 };
 
 static struct clk_sources clkset_uhost = {
@@ -243,8 +318,8 @@
 		return -EINVAL;
 
 	val = __raw_readl(reg);
-	val &= ~(0xf << sclk->shift);
-	val |= (div - 1) << sclk->shift;
+	val &= ~(0xf << sclk->divider_shift);
+	val |= (div - 1) << sclk->divider_shift;
 	__raw_writel(val, reg);
 
 	return 0;
@@ -284,7 +359,7 @@
 	if (rate > parent_rate)
 		rate = parent_rate;
 	else {
-		div = rate / parent_rate;
+		div = parent_rate / rate;
 
 		if (div == 0)
 			div = 1;
@@ -520,6 +595,55 @@
 	.reg_divider	= S3C_CLK_DIV2,
 };
 
+static struct clk *clkset_camera_list[] = {
+	&clk_h2,
+};
+
+static struct clk_sources clkset_camera = {
+	.sources	= clkset_camera_list,
+	.nr_sources	= ARRAY_SIZE(clkset_camera_list),
+};
+
+static struct clksrc_clk clk_camera = {
+	.clk	= {
+		.name		= "camera",
+		.id		= -1,
+		.ctrlbit        = S3C_CLKCON_SCLK_CAM,
+		.enable		= s3c64xx_sclk_ctrl,
+		.set_parent	= s3c64xx_setparent_clksrc,
+		.get_rate	= s3c64xx_getrate_clksrc,
+		.set_rate	= s3c64xx_setrate_clksrc,
+		.round_rate	= s3c64xx_roundrate_clksrc,
+	},
+	.shift		= 0,
+	.mask		= 0,
+	.sources	= &clkset_camera,
+	.divider_shift	= S3C6400_CLKDIV0_CAM_SHIFT,
+	.reg_divider	= S3C_CLK_DIV0,
+};
+
+static struct clk *clkset_camif_list[] = {
+	&clk_h,
+};
+
+static struct clk_sources clkset_camif = {
+	.sources	= clkset_camif_list,
+	.nr_sources	= ARRAY_SIZE(clkset_camif_list),
+};
+
+static struct clksrc_clk clk_camif = {
+	.clk	= {
+		.name		= "camif",
+		.id		= -1,
+		.ctrlbit        = S3C_CLKCON_HCLK_CAMIF,
+		.enable		= s3c64xx_hclk_ctrl,
+		.set_parent	= s3c64xx_setparent_clksrc,
+	},
+	.shift		= 0,
+	.mask		= 0,
+	.sources	= &clkset_camif,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -536,6 +660,8 @@
 	&clk_audio0,
 	&clk_audio1,
 	&clk_irda,
+	&clk_camif,
+	&clk_camera,
 };
 
 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
@@ -608,6 +734,7 @@
 	clk_fout_epll.rate = epll;
 	clk_fout_apll.rate = apll;
 
+	clk_h2.rate = hclk2;
 	clk_h.rate = hclk;
 	clk_p.rate = pclk;
 	clk_f.rate = fclk;
@@ -635,6 +762,9 @@
 	&clk_audio0.clk,
 	&clk_audio1.clk,
 	&clk_irda.clk,
+	&clk_camera.clk,
+	&clk_camif.clk,
+	&clk_arm,
 };
 
 void __init s3c6400_register_clocks(void)
@@ -652,6 +782,5 @@
 		}
 	}
 
-	clk_mpll.parent = &clk_mout_mpll.clk;
 	clk_epll.parent = &clk_mout_epll.clk;
 }
diff -urN android_2.6.29_org/arch/arm/plat-s3c64xx/sleep.S android_2.6.29/arch/arm/plat-s3c64xx/sleep.S
--- android_2.6.29_org/arch/arm/plat-s3c64xx/sleep.S	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/arch/arm/plat-s3c64xx/sleep.S	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,143 @@
+/* linux/0arch/arm/plat-s3c64xx/sleep.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU sleep code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/map.h>
+
+#undef S3C64XX_VA_GPIO
+#define S3C64XX_VA_GPIO (0x0)
+
+#include <plat/regs-gpio.h>
+#include <plat/gpio-bank-n.h>
+
+#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
+
+	.text
+
+	/* s3c_cpu_save
+	 *
+	 * Save enough processor state to allow the restart of the pm.c
+	 * code after resume.
+	 *
+	 * entry:
+	 *	r0 = pointer to the save block
+	 * exit:
+	 *	r0 = exit code: 1 => stored data
+	 *			0 => resumed from sleep
+	*/
+
+ENTRY(s3c_cpu_save)
+	stmfd	sp!, { r4 - r12, lr }
+
+	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
+	mrc	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
+	mrc	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
+	mrc	p15, 0, r8, c2, c0, 2	@ Translation Table Control
+	mrc	p15, 0, r9, c1, c0, 0	@ Control register
+	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
+	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
+
+	stmia	r0, { r4 - r13 }	@ Save CP registers and SP
+	mov	r0, #0
+	ldmfd	sp, { r4 - r12, pc }	@ return, not disturbing SP
+
+	@@ return to the caller, after the MMU is turned on.
+	@@ restore the last bits of the stack and return.
+resume_with_mmu:
+	mov	r0, #1
+	ldmfd	sp!, { r4 - r12, pc }	@ return, from sp from s3c_cpu_save
+
+	.data
+
+	/* the next bit is code, but it requires easy access to the
+	 * s3c_sleep_save_phys data before the MMU is switched on, so
+	 * we store the code that needs this variable in the .data where
+	 * the value can be written to (the .text segment is RO).
+	*/
+
+	.global	s3c_sleep_save_phys
+s3c_sleep_save_phys:
+	.word	0
+
+	/* Sleep magic, the word before the resume entry point so that the
+	 * bootloader can check for a resumeable image. */
+
+	.word	0x2bedf00d
+
+	/* s3c_cpu_reusme
+	 *
+	 * This is the entry point, stored by whatever method the bootloader
+	 * requires to get the kernel runnign again. This code expects to be
+	 * entered with no caches live and the MMU disabled. It will then
+	 * restore the MMU and other basic CP registers saved and restart
+	 * the kernel C code to finish the resume code.
+	*/
+
+ENTRY(s3c_cpu_resume)
+	msr	cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+	ldr	r2, =LL_UART		/* for debug */
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+	/* Initialise the GPIO state if we are debugging via the SMDK LEDs,
+	 * as the uboot version supplied resets these to inputs during the
+	 * resume checks.
+	*/
+
+	ldr	r3, =S3C64XX_PA_GPIO
+	ldr	r0, [ r3, #S3C64XX_GPNCON ]
+	bic	r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
+			  S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
+	orr	r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
+			  S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
+	str	r0, [ r3, #S3C64XX_GPNCON ]
+
+	ldr	r0, [ r3, #S3C64XX_GPNDAT ]
+	bic	r0, r0, #0xf << 12			@ GPN12..15
+	orr	r0, r0, #1 << 15			@ GPN15
+	str	r0, [ r3, #S3C64XX_GPNDAT ]
+#endif
+
+	/* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
+	 * are thoroughly cleaned just in case the bootloader didn't do it
+	 * for us. */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
+	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
+	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
+	@@mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
+	@@mcr	p15, 0, r0, c7, c7, 0		@ Invalidate I + D caches
+
+	ldr	r0, s3c_sleep_save_phys
+	ldmia	r0, { r4 - r13 }
+
+	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
+	mcr	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
+	mcr	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
+	mcr	p15, 0, r8, c2, c0, 2	@ Translation Table Control
+	mcr	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
+
+	mov	r0, #0			@ restore copro access controls
+	mcr	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
+	mcr 	p15, 0, r0, c7, c5, 4
+
+	ldr	r2, =resume_with_mmu
+	mcr	p15, 0, r9, c1, c0, 0		/* turn mmu back on */
+	nop
+	mov	pc, r2				/* jump back */
+
+	.end
diff -urN android_2.6.29_org/drivers/i2c/busses/Kconfig android_2.6.29/drivers/i2c/busses/Kconfig
--- android_2.6.29_org/drivers/i2c/busses/Kconfig	2009-04-20 13:34:53.000000000 +0900
+++ android_2.6.29/drivers/i2c/busses/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -455,11 +455,12 @@
 	  I2C bus.
 
 config I2C_S3C2410
-	tristate "S3C2410 I2C Driver"
-	depends on ARCH_S3C2410
-	help
-	  Say Y here to include support for I2C controller in the
-	  Samsung S3C2410 based System-on-Chip devices.
+        tristate "Samsung SoC I2C Driver (S3C24XX and S3C64XX series)"
+        depends on ARCH_S3C2410 || ARCH_S3C64XX
+        help
+          Say Y here to include support for I2C controller in the
+          Samsung S3C based System-on-Chip devices such as the S3C2410,
+          S3C2440, S3C2442, S3C2443 and S3C6410.
 
 config I2C_SH7760
 	tristate "Renesas SH7760 I2C Controller"
diff -urN android_2.6.29_org/drivers/input/touchscreen/Kconfig android_2.6.29/drivers/input/touchscreen/Kconfig
--- android_2.6.29_org/drivers/input/touchscreen/Kconfig	2009-04-20 13:34:53.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -78,6 +78,29 @@
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called fujitsu-ts.
+config TOUCHSCREEN_S3C
+        tristate "S3C touchscreen driver"
+        depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC1XX
+        default y
+        help
+          Say Y here to enable the driver for the touchscreen on the
+          S3C SMDK board.
+
+          If unsure, say N.
+
+          To compile this driver as a module, choose M here: the
+          module will be called s3c_ts.
+
+config TOUCHSCREEN_NEW
+        bool "new flip touch"
+        depends on TOUCHSCREEN_S3C
+        default y
+        help
+          Say Y here to enable the driver for the new version touchscreen on the
+          S3C SMDK board.
+
+          Say N here to enable the driver for the old version touchscreen on the
+          S3C SMDK board.
 
 config TOUCHSCREEN_GUNZE
 	tristate "Gunze AHL-51S touchscreen"
diff -urN android_2.6.29_org/drivers/input/touchscreen/Makefile android_2.6.29/drivers/input/touchscreen/Makefile
--- android_2.6.29_org/drivers/input/touchscreen/Makefile	2009-04-20 13:34:53.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/Makefile	2009-04-10 12:41:06.000000000 +0900
@@ -35,3 +35,4 @@
 wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712)	+= wm9712.o
 wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713)	+= wm9713.o
 obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE)	+= mainstone-wm97xx.o
+obj-$(CONFIG_TOUCHSCREEN_S3C) 		+= s3c-ts.o key_driver.o
diff -urN android_2.6.29_org/drivers/input/touchscreen/key_driver.c android_2.6.29/drivers/input/touchscreen/key_driver.c
--- android_2.6.29_org/drivers/input/touchscreen/key_driver.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/key_driver.c	2009-04-10 12:40:33.000000000 +0900
@@ -0,0 +1,280 @@
+/*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*
+*
+*/
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+
+#include <linux/platform_device.h>
+#include <plat/regs-gpio.h>
+
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+/* For id.version */
+#define NEADBUTVERSION        0x0001
+#define DRV_NAME                "nead-buttons"
+
+//#define REPEAT_DELAY                HZ/10
+#define BUTTON_DELAY                 (HZ/25)       /* 4: 40ms */
+
+#define KEY_RELEASED            0
+#define KEY_PRESSED             1
+
+//#define GDEBUG
+#ifdef GDEBUG
+#    define dprintk(msg...) printk("nead_buttons: " msg);
+#else
+#    define dprintk(msg...)
+#endif
+
+static struct timer_list button_check_timer;
+
+struct nead_button
+{
+    int             pin;
+    int             pin_setting;
+    int             keycode;
+    char           *name;
+    int             last_state;
+};
+
+/* key definition => include/linux/input.h */     
+#define NUM_OF_BUTTONS          4
+static struct nead_button nead_buttons[] = {
+    {S3C64XX_GPN(0), S3C_GPIO_INPUT, KEY_PHONE, "1", 0},
+    {S3C64XX_GPN(1), S3C_GPIO_INPUT, KEY_BACK, "2", 0},
+    {S3C64XX_GPN(2), S3C_GPIO_INPUT, KEY_F1, "3", 0},
+    {S3C64XX_GPN(3), S3C_GPIO_INPUT, KEY_F2, "4", 0},
+};
+
+struct nead_buttons_private
+{
+    struct input_dev *input;
+    spinlock_t      lock;
+    int             count;
+    int             shift;
+    char            phys[32];
+};
+
+struct nead_buttons_private        *nead_buttons_private;
+
+static void neadkey_timer_callback(unsigned long data)
+{
+    struct nead_button *button = (struct nead_button *) data;
+    unsigned long flags;
+    int             i;
+    int             pre_status;
+
+
+    local_irq_save(flags);
+
+    for (i = 0; i < NUM_OF_BUTTONS; i++) 
+    {
+        pre_status = button->last_state;
+
+	button->last_state = s3c_gpio_getpin(button->pin) ? KEY_RELEASED : KEY_PRESSED;
+
+        if (pre_status == button->last_state)
+        {
+            button++;
+            continue;
+        }
+
+        //printk("%s, status:%d\n", button->name, button->last_state);
+
+        input_report_key(nead_buttons_private->input, button->keycode, button->last_state);
+       
+        input_sync(nead_buttons_private->input);
+
+        button++;
+    }
+    local_irq_restore(flags);
+
+#if 0
+{
+int gpn_con = readl(0xf4500180);
+int gpn_data = readl(0xf4500184);
+int gpn_pud = readl(0xf4500188);
+int gpn_smcon = readl(0xf450018c);
+int gpn_smpud = readl(0xf4500190);
+printk("!@# GPN %x %x %x %x %x\n", gpn_con, gpn_data, gpn_pud, gpn_smcon, gpn_smpud);
+}
+#endif
+    mod_timer(&button_check_timer, jiffies + (BUTTON_DELAY));
+    
+}
+
+
+static int __devinit neadkey_probe(struct platform_device *pdev)
+{
+    
+    struct input_dev *input_dev;
+    
+    int error;
+    int  i;
+    
+    nead_buttons_private = kzalloc(sizeof(struct nead_buttons_private), GFP_KERNEL);
+    input_dev = input_allocate_device();
+    
+    if (!nead_buttons_private || !input_dev) {
+                error = -ENOMEM;
+                goto fail;
+    }
+        
+    platform_set_drvdata(pdev, nead_buttons_private);
+    
+    nead_buttons_private->input = input_dev;
+            
+    input_dev->evbit[0] = BIT(EV_KEY) ;
+    input_dev->dev.parent = &pdev->dev ;
+    input_dev->name = DRV_NAME;
+    input_dev->phys = "nead_buttons";
+    input_dev->id.bustype = BUS_HOST;
+    input_dev->id.vendor = 0xDEAD;
+    input_dev->id.product = 0xBEEF;
+    input_dev->id.version = NEADBUTVERSION;
+
+    for (i = 0; i < ARRAY_SIZE(nead_buttons); i++)
+    {
+        set_bit(nead_buttons[i].keycode, input_dev->keybit);
+
+        s3c_gpio_cfgpin(nead_buttons[i].pin, nead_buttons[i].pin_setting);
+        s3c_gpio_setpull(nead_buttons[i].pin, 1);
+    }
+
+    init_timer(&button_check_timer);
+    button_check_timer.function = neadkey_timer_callback;
+    button_check_timer.data = (unsigned long) &nead_buttons[0];
+
+    button_check_timer.expires = jiffies + (BUTTON_DELAY);
+    add_timer(&button_check_timer);
+
+    printk(KERN_INFO "%s successfully loaded\n", DRV_NAME);
+
+    /*
+     * All went ok, so register to the input system 
+     */
+    input_register_device(nead_buttons_private->input);
+
+    return 0;
+    
+fail:        
+		kfree(nead_buttons_private);
+        input_free_device(input_dev);
+        return error;    
+}
+
+static int __devexit neadkey_remove(struct platform_device *pdev)
+{
+    int i;
+    struct nead_buttons_private *nead_buttons_private_temp = platform_get_drvdata(pdev);
+
+    for (i = 0; i < ARRAY_SIZE(nead_buttons); i++)
+	gpio_free(nead_buttons[i].pin);
+ 
+    del_timer(&button_check_timer);
+    input_unregister_device(nead_buttons_private_temp->input);
+    kfree(nead_buttons_private_temp);
+    return 0;
+}
+
+#ifdef CONFIG_PM
+static int neadkey_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+static int neadkey_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define neadkey_suspend NULL
+#define neadkey_resume  NULL
+#endif
+
+
+static struct platform_driver neadkey_driver = {
+	.driver         = {
+		.name   = "nead-button",
+		.owner  = THIS_MODULE,
+		},
+		.probe          = neadkey_probe,
+		.remove         = neadkey_remove,
+		.suspend        = neadkey_suspend,
+		.resume         = neadkey_resume,
+};
+
+static void neadkey_platform_release(struct device *device)
+{
+}
+
+static struct platform_device neadkey_device = {
+	.name	= "nead-button",
+	.id	= 0,
+	.dev	= {
+	.release = neadkey_platform_release
+	}
+};
+
+int __init        neadkey_init(void)
+{
+	int res;
+	res = platform_device_register(&neadkey_device);
+	if(res)
+	{
+		printk("fail : platform device %s (%d) \n", neadkey_device.name, res);
+		return res;
+	}
+
+	res =  platform_driver_register(&neadkey_driver);
+	if(res)
+	{
+		printk("fail : platrom driver %s (%d) \n", neadkey_driver.driver.name, res);
+		return res;
+	}
+	
+	return 0;
+}
+
+void __exit  neadkey_exit(void)
+{
+	printk("it cleaned\n");
+	platform_driver_unregister(&neadkey_driver);
+	platform_device_unregister(&neadkey_device);
+}
+
+module_init(neadkey_init);
+module_exit(neadkey_exit);
+
+
+
+MODULE_AUTHOR("nemus");
+MODULE_DESCRIPTION("nead buttons driver");
+MODULE_LICENSE("GPL");
+
diff -urN android_2.6.29_org/drivers/input/touchscreen/key_driver_smb380.c android_2.6.29/drivers/input/touchscreen/key_driver_smb380.c
--- android_2.6.29_org/drivers/input/touchscreen/key_driver_smb380.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/key_driver_smb380.c	2009-04-13 15:29:38.000000000 +0900
@@ -0,0 +1,344 @@
+/*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*
+*
+*/
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+
+#include <linux/platform_device.h>
+#include <plat/regs-gpio.h>
+
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+#include "smb380.h"
+#include "smb380.c"
+
+/* For id.version */
+#define NEADBUTVERSION        0x0001
+#define DRV_NAME                "nead-buttons"
+
+//#define REPEAT_DELAY                HZ/10
+#define BUTTON_DELAY                 (HZ/25)       /* 4: 40ms */
+
+#define KEY_RELEASED            0
+#define KEY_PRESSED             1
+
+//#define GDEBUG
+#ifdef GDEBUG
+#    define dprintk(msg...) printk("nead_buttons: " msg);
+#else
+#    define dprintk(msg...)
+#endif
+
+static struct timer_list button_check_timer;
+
+struct nead_button
+{
+    int             pin;
+    int             pin_setting;
+    int             keycode;
+    char           *name;
+    int             last_state;
+};
+
+/* key definition => include/linux/input.h */     
+#define NUM_OF_BUTTONS          4
+static struct nead_button nead_buttons[] = {
+    {S3C64XX_GPN(0), S3C_GPIO_INPUT, KEY_PHONE, "1", 0},
+    {S3C64XX_GPN(1), S3C_GPIO_INPUT, KEY_BACK, "2", 0},
+    {S3C64XX_GPN(2), S3C_GPIO_INPUT, KEY_F1, "3", 0},
+    {S3C64XX_GPN(3), S3C_GPIO_INPUT, KEY_F2, "4", 0},
+};
+
+struct nead_buttons_private
+{
+    struct input_dev *input;
+    spinlock_t      lock;
+    int             count;
+    int             shift;
+    char            phys[32];
+};
+
+struct nead_buttons_private        *nead_buttons_private;
+
+static void neadkey_timer_callback(unsigned long data)
+{
+    struct nead_button *button = (struct nead_button *) data;
+    unsigned long flags;
+    int             i;
+    int             pre_status;
+
+
+    local_irq_save(flags);
+
+    for (i = 0; i < NUM_OF_BUTTONS; i++) 
+    {
+        pre_status = button->last_state;
+
+	button->last_state = s3c_gpio_getpin(button->pin) ? KEY_RELEASED : KEY_PRESSED;
+
+        if (pre_status == button->last_state)
+        {
+            button++;
+            continue;
+        }
+
+        //printk("%s, status:%d\n", button->name, button->last_state);
+
+        input_report_key(nead_buttons_private->input, button->keycode, button->last_state);
+       
+        input_sync(nead_buttons_private->input);
+
+        button++;
+    }
+    local_irq_restore(flags);
+
+#if 0
+{
+int gpn_con = readl(0xf4500180);
+int gpn_data = readl(0xf4500184);
+int gpn_pud = readl(0xf4500188);
+int gpn_smcon = readl(0xf450018c);
+int gpn_smpud = readl(0xf4500190);
+printk("!@# GPN %x %x %x %x %x\n", gpn_con, gpn_data, gpn_pud, gpn_smcon, gpn_smpud);
+}
+#endif
+    mod_timer(&button_check_timer, jiffies + (BUTTON_DELAY));
+    
+}
+
+smb380_t smb380;
+smb380_t *p_smb380 = &smb380;
+
+int i2c_bus_write(unsigned char dev_addr, unsigned char reg_addr, unsigned char * data, unsigned char datasize)
+{
+
+	if(datasize > 127){
+		printk("I2C write: datasize is too large\n")));
+		return -1;
+	}
+
+    DWORD dwErr;
+
+    // use the driver-to-driver call
+    dwErr = p_smb380->fc.I2CWrite(p_smb380->fc.Context,
+                              (SMB380_I2C_ADDR << 1),   	// SlaveAddress
+                              reg_addr,         // WordAddress
+                              data,
+                              datasize);
+
+    if ( dwErr ) {
+        RETAILMSG(SMB_ERR_0, (TEXT("I2CWrite ERROR: %u \r\n"), dwErr));
+    }
+    LeaveCriticalSection(&g_csSMB);
+
+    return dwErr;
+}
+
+int i2c_bus_read(unsigned char dev_addr, unsigned char reg_addr, unsigned char * data, unsigned char datasize)
+{
+
+	if(datasize > 127){
+		RETAILMSG(SMB_ERR_0, (TEXT("I2C read: datasize is too large\r\n")));
+		return -1;
+	}
+    DWORD dwErr;
+
+    // use the driver-to-driver call
+    RETAILMSG(SMB_DBG_1,(TEXT("i2c_bus_read[%x]: 0x%X, 0x%X, %u\r\n"), p_smb380->fc.Context, reg_addr, data, datasize));
+    EnterCriticalSection(&g_csSMB);
+    dwErr = p_smb380->fc.I2CRead(p_smb380->fc.Context,
+                             (SMB380_I2C_ADDR << 1) + 1, 	// SlaveAddress
+                             reg_addr,      // WordAddress
+                             data,
+                             datasize);
+    
+    if ( !dwErr ) {
+	;
+    } else {        
+        RETAILMSG(SMB_ERR_0,(TEXT("I2CRead ERROR: %u \r\n"), dwErr));
+    }
+    LeaveCriticalSection(&g_csSMB);
+    
+    return dwErr;
+}
+
+static int __devinit neadkey_probe(struct platform_device *pdev)
+{
+    
+    struct input_dev *input_dev;
+    
+    int error;
+    int  i;
+    
+    nead_buttons_private = kzalloc(sizeof(struct nead_buttons_private), GFP_KERNEL);
+
+p_smb380->dev_addr = 0x38;
+p_smb380->delay_msec = msleep;
+p_smb380->bus_write  = i2c_bus_write;
+p_smb380->bus_read  = i2c_bus_read;
+    
+    input_dev = input_allocate_device();
+    
+    if (!nead_buttons_private || !input_dev) {
+                error = -ENOMEM;
+                goto fail;
+    }
+        
+    platform_set_drvdata(pdev, nead_buttons_private);
+    
+    nead_buttons_private->input = input_dev;
+            
+    input_dev->evbit[0] = BIT(EV_KEY) ;
+    input_dev->dev.parent = &pdev->dev ;
+    input_dev->name = DRV_NAME;
+    input_dev->phys = "nead_buttons";
+    input_dev->id.bustype = BUS_HOST;
+    input_dev->id.vendor = 0xDEAD;
+    input_dev->id.product = 0xBEEF;
+    input_dev->id.version = NEADBUTVERSION;
+
+    for (i = 0; i < ARRAY_SIZE(nead_buttons); i++)
+    {
+        set_bit(nead_buttons[i].keycode, input_dev->keybit);
+
+        s3c_gpio_cfgpin(nead_buttons[i].pin, nead_buttons[i].pin_setting);
+        s3c_gpio_setpull(nead_buttons[i].pin, 1);
+    }
+
+    init_timer(&button_check_timer);
+    button_check_timer.function = neadkey_timer_callback;
+    button_check_timer.data = (unsigned long) &nead_buttons[0];
+
+    button_check_timer.expires = jiffies + (BUTTON_DELAY);
+    add_timer(&button_check_timer);
+
+    printk(KERN_INFO "%s successfully loaded\n", DRV_NAME);
+
+    /*
+     * All went ok, so register to the input system 
+     */
+    input_register_device(nead_buttons_private->input);
+
+    return 0;
+    
+fail:        
+		kfree(nead_buttons_private);
+        input_free_device(input_dev);
+        return error;    
+}
+
+static int __devexit neadkey_remove(struct platform_device *pdev)
+{
+    int i;
+    struct nead_buttons_private *nead_buttons_private_temp = platform_get_drvdata(pdev);
+
+    for (i = 0; i < ARRAY_SIZE(nead_buttons); i++)
+	gpio_free(nead_buttons[i].pin);
+ 
+    del_timer(&button_check_timer);
+    input_unregister_device(nead_buttons_private_temp->input);
+    kfree(nead_buttons_private_temp);
+    return 0;
+}
+
+#ifdef CONFIG_PM
+static int neadkey_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+static int neadkey_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define neadkey_suspend NULL
+#define neadkey_resume  NULL
+#endif
+
+
+static struct platform_driver neadkey_driver = {
+	.driver         = {
+		.name   = "nead-button",
+		.owner  = THIS_MODULE,
+		},
+		.probe          = neadkey_probe,
+		.remove         = neadkey_remove,
+		.suspend        = neadkey_suspend,
+		.resume         = neadkey_resume,
+};
+
+static void neadkey_platform_release(struct device *device)
+{
+}
+
+static struct platform_device neadkey_device = {
+	.name	= "nead-button",
+	.id	= 0,
+	.dev	= {
+	.release = neadkey_platform_release
+	}
+};
+
+int __init        neadkey_init(void)
+{
+	int res;
+	res = platform_device_register(&neadkey_device);
+	if(res)
+	{
+		printk("fail : platform device %s (%d) \n", neadkey_device.name, res);
+		return res;
+	}
+
+	res =  platform_driver_register(&neadkey_driver);
+	if(res)
+	{
+		printk("fail : platrom driver %s (%d) \n", neadkey_driver.driver.name, res);
+		return res;
+	}
+	
+	return 0;
+}
+
+void __exit  neadkey_exit(void)
+{
+	printk("it cleaned\n");
+	platform_driver_unregister(&neadkey_driver);
+	platform_device_unregister(&neadkey_device);
+}
+
+module_init(neadkey_init);
+module_exit(neadkey_exit);
+
+
+
+MODULE_AUTHOR("nemus");
+MODULE_DESCRIPTION("nead buttons driver");
+MODULE_LICENSE("GPL");
+
diff -urN android_2.6.29_org/drivers/input/touchscreen/s3c-ts.c android_2.6.29/drivers/input/touchscreen/s3c-ts.c
--- android_2.6.29_org/drivers/input/touchscreen/s3c-ts.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/s3c-ts.c	2009-04-17 15:59:25.000000000 +0900
@@ -0,0 +1,533 @@
+/* linux/drivers/input/touchscreen/s3c-ts.c
+ *
+ * $Id: s3c-ts.c,v 1.13 2008/11/20 06:00:55 ihlee215 Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * iPAQ H1940 touchscreen support
+ *
+ * ChangeLog
+ *
+ * 2004-09-05: Herbert Potzl <herbert@13thfloor.at>
+ *	- added clock (de-)allocation code
+ *
+ * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
+ *      - h1940_ -> s3c24xx (this driver is now also used on the n30
+ *        machines :P)
+ *      - Debug messages are now enabled with the config option
+ *        TOUCHSCREEN_S3C_DEBUG
+ *      - Changed the way the value are read
+ *      - Input subsystem should now work
+ *      - Use ioremap and readl/writel
+ *
+ * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
+ *      - Make use of some undocumented features of the touchscreen
+ *        controller
+ *
+ * 2006-09-05: Ryu Euiyoul <ryu.real@gmail.com>
+ *      - added power management suspend and resume code
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/init.h>
+#include <linux/serio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-adc.h>
+#include <plat/ts.h>
+#include <mach/irqs.h>
+
+#define CONFIG_TOUCHSCREEN_S3C_DEBUG
+#undef CONFIG_TOUCHSCREEN_S3C_DEBUG
+
+/* For ts->dev.id.version */
+#define S3C_TSVERSION	0x0101
+
+#define WAIT4INT(x)  (((x)<<8) | \
+		     S3C_ADCTSC_YM_SEN | S3C_ADCTSC_YP_SEN | S3C_ADCTSC_XP_SEN | \
+		     S3C_ADCTSC_XY_PST(3))
+
+#define AUTOPST	     (S3C_ADCTSC_YM_SEN | S3C_ADCTSC_YP_SEN | S3C_ADCTSC_XP_SEN | \
+		     S3C_ADCTSC_AUTO_PST | S3C_ADCTSC_XY_PST(0))
+
+
+#define DEBUG_LVL    KERN_DEBUG
+
+
+/* Touchscreen default configuration */
+struct s3c_ts_mach_info s3c_ts_default_cfg __initdata = {
+                .delay = 		10000,
+                .presc = 		49,
+                .oversampling_shift = 	2,
+		.resol_bit = 		10
+};
+
+/*
+ * Definitions & global arrays.
+ */
+static char *s3c_ts_name = "S3C TouchScreen";
+static void __iomem 		*ts_base;
+static struct resource		*ts_mem;
+static struct resource		*ts_irq;
+static struct clk		*ts_clock;
+static struct s3c_ts_info 	*ts;
+
+static void touch_timer_fire(unsigned long data)
+{
+	unsigned long data0;
+	unsigned long data1;
+	int updown;
+
+	data0 = readl(ts_base+S3C_ADCDAT0);
+	data1 = readl(ts_base+S3C_ADCDAT1);
+
+	updown = (!(data0 & S3C_ADCDAT0_UPDOWN)) && (!(data1 & S3C_ADCDAT1_UPDOWN));
+
+	if (updown) {
+		if (ts->count) {
+
+#ifdef CONFIG_TOUCHSCREEN_S3C_DEBUG
+			{
+				struct timeval tv;
+				do_gettimeofday(&tv);
+				printk(KERN_INFO "T: %06d, X: %03ld, Y: %03ld\n", (int)tv.tv_usec, ts->xp, ts->yp);
+			}
+#endif
+
+#if 1
+{
+#ifdef ALPHA_BOARD
+	static int pointercal[7]={-8, -5258, 67843504, -4626, 6, 53654464, 65536};
+#else
+	static int pointercal[7]={-13, -5277, 68214248, 5720, 47, -32546824, 65536};
+#endif
+	int prev_X,prev_Y;  int xtemp,ytemp;   
+	int x, y;
+	x = ts->xp; y = ts->yp;
+	xtemp = x; ytemp = y;
+ 
+	x = ( pointercal[2] + pointercal[0]*xtemp + pointercal[1]*ytemp ) / pointercal[6];
+	y = ( pointercal[5] + pointercal[3]*xtemp + pointercal[4]*ytemp ) / pointercal[6];
+ 
+	if (x>800 || x < 0 )
+		x=prev_X;    
+	if (y>480 || y < 0 ) 
+		y=prev_Y;
+
+	prev_X = x;    
+	prev_Y = y;
+    
+	if (x<800 && x >=0)
+	{
+		input_report_abs(ts->dev, ABS_X, x);
+		input_report_abs(ts->dev, ABS_Y, y);
+		//printk("Android Touch ABS : %d %d %d, %d\n", xtemp, ytemp, x,y);   
+	}
+}
+#else
+			input_report_abs(ts->dev, ABS_X, ts->xp);
+			input_report_abs(ts->dev, ABS_Y, ts->yp);
+#endif
+			input_report_key(ts->dev, BTN_TOUCH, 1);
+			input_report_abs(ts->dev, ABS_PRESSURE, 1);
+			input_sync(ts->dev);
+		}
+
+		ts->xp = 0;
+		ts->yp = 0;
+		ts->count = 0;
+
+		writel(S3C_ADCTSC_PULL_UP_DISABLE | AUTOPST, ts_base+S3C_ADCTSC);
+		writel(readl(ts_base+S3C_ADCCON) | S3C_ADCCON_ENABLE_START, ts_base+S3C_ADCCON);
+	}
+	else {
+
+		ts->count = 0;
+
+		input_report_key(ts->dev, BTN_TOUCH, 0);
+		input_report_abs(ts->dev, ABS_PRESSURE, 0);
+		input_sync(ts->dev);
+
+		writel(WAIT4INT(0), ts_base+S3C_ADCTSC);
+	}
+}
+
+static struct timer_list touch_timer =
+		TIMER_INITIALIZER(touch_timer_fire, 0, 0);
+
+static irqreturn_t stylus_updown(int irqno, void *param)
+{
+	unsigned long data0;
+	unsigned long data1;
+	int updown;
+
+	data0 = readl(ts_base+S3C_ADCDAT0);
+	data1 = readl(ts_base+S3C_ADCDAT1);
+
+	updown = (!(data0 & S3C_ADCDAT0_UPDOWN)) && (!(data1 & S3C_ADCDAT1_UPDOWN));
+
+#ifdef CONFIG_TOUCHSCREEN_S3C_DEBUG
+       printk(KERN_INFO "   %c\n",	updown ? 'D' : 'U');
+#endif
+
+	/* TODO we should never get an interrupt with updown set while
+	 * the timer is running, but maybe we ought to verify that the
+	 * timer isn't running anyways. */
+
+	if (updown)
+		touch_timer_fire(0);
+
+	if(ts->s3c_adc_con==ADC_TYPE_2) {
+       		__raw_writel(0x0, ts_base+S3C_ADCCLRWK);
+        	__raw_writel(0x0, ts_base+S3C_ADCCLRINT);
+	}
+        
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t stylus_action(int irqno, void *param)
+{
+	unsigned long data0;
+	unsigned long data1;
+
+	data0 = readl(ts_base+S3C_ADCDAT0);
+	data1 = readl(ts_base+S3C_ADCDAT1);
+
+	if(ts->resol_bit==12) {
+#if defined(CONFIG_TOUCHSCREEN_NEW)
+		ts->yp += S3C_ADCDAT0_XPDATA_MASK_12BIT - (data0 & S3C_ADCDAT0_XPDATA_MASK_12BIT);
+		ts->xp += S3C_ADCDAT1_YPDATA_MASK_12BIT - (data1 & S3C_ADCDAT1_YPDATA_MASK_12BIT);
+#else 
+		ts->xp += data0 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
+		ts->yp += data1 & S3C_ADCDAT1_YPDATA_MASK_12BIT;
+#endif
+	}
+	else {
+#if defined(CONFIG_TOUCHSCREEN_NEW)
+		ts->yp += S3C_ADCDAT0_XPDATA_MASK - (data0 & S3C_ADCDAT0_XPDATA_MASK);
+		ts->xp += S3C_ADCDAT1_YPDATA_MASK - (data1 & S3C_ADCDAT1_YPDATA_MASK);
+#else
+		ts->xp += data0 & S3C_ADCDAT0_XPDATA_MASK;
+		ts->yp += data1 & S3C_ADCDAT1_YPDATA_MASK;
+#endif	
+	}
+
+	ts->count++;
+
+	if (ts->count < (1<<ts->shift)) {
+		writel(S3C_ADCTSC_PULL_UP_DISABLE | AUTOPST, ts_base+S3C_ADCTSC);
+		writel(readl(ts_base+S3C_ADCCON) | S3C_ADCCON_ENABLE_START, ts_base+S3C_ADCCON);
+	} else {
+		mod_timer(&touch_timer, jiffies+1);
+		writel(WAIT4INT(1), ts_base+S3C_ADCTSC);
+	}
+
+	if(ts->s3c_adc_con==ADC_TYPE_2) {
+       		__raw_writel(0x0, ts_base+S3C_ADCCLRWK);
+        	__raw_writel(0x0, ts_base+S3C_ADCCLRINT);
+	}
+	
+	return IRQ_HANDLED;
+}
+
+
+static struct s3c_ts_mach_info *s3c_ts_get_platdata (struct device *dev)
+{
+	if (dev->platform_data != NULL)
+		return (struct s3c_ts_mach_info *)dev->platform_data;
+
+	return &s3c_ts_default_cfg;
+}
+
+/*
+ * The functions for inserting/removing us as a module.
+ */
+static int __init s3c_ts_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct device *dev;
+	struct input_dev *input_dev;
+	struct s3c_ts_mach_info * s3c_ts_cfg;
+	int ret, size;
+
+	dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev,"no memory resource specified\n");
+		return -ENOENT;
+	}
+
+	size = (res->end - res->start) + 1;
+	ts_mem = request_mem_region(res->start, size, pdev->name);
+	if (ts_mem == NULL) {
+		dev_err(dev, "failed to get memory region\n");
+		ret = -ENOENT;
+		goto err_req;
+	}
+
+	ts_base = ioremap(res->start, size);
+	if (ts_base == NULL) {
+		dev_err(dev, "failed to ioremap() region\n");
+		ret = -EINVAL;
+		goto err_map;
+	}
+	
+	ts_clock = clk_get(&pdev->dev, "adc");
+	if (IS_ERR(ts_clock)) {
+		dev_err(dev, "failed to find watchdog clock source\n");
+		ret = PTR_ERR(ts_clock);
+		goto err_clk;
+	}
+
+	clk_enable(ts_clock);
+
+	s3c_ts_cfg = s3c_ts_get_platdata(&pdev->dev);
+		
+	if ((s3c_ts_cfg->presc&0xff) > 0)
+		writel(S3C_ADCCON_PRSCEN | S3C_ADCCON_PRSCVL(s3c_ts_cfg->presc&0xFF),\
+				ts_base+S3C_ADCCON);
+	else
+		writel(0, ts_base+S3C_ADCCON);
+
+
+	/* Initialise registers */
+	if ((s3c_ts_cfg->delay&0xffff) > 0)
+		writel(s3c_ts_cfg->delay & 0xffff, ts_base+S3C_ADCDLY);
+
+	if (s3c_ts_cfg->resol_bit==12) {
+		switch(s3c_ts_cfg->s3c_adc_con) {
+		case ADC_TYPE_2:
+			writel(readl(ts_base+S3C_ADCCON)|S3C_ADCCON_RESSEL_12BIT, ts_base+S3C_ADCCON);
+			break;
+
+		case ADC_TYPE_1:
+			writel(readl(ts_base+S3C_ADCCON)|S3C_ADCCON_RESSEL_12BIT_1, ts_base+S3C_ADCCON);
+			break;
+			
+		default:
+			dev_err(dev, "Touchscreen over this type of AP isn't supported !\n");
+			break;
+		}
+	}
+	
+	writel(WAIT4INT(0), ts_base+S3C_ADCTSC);
+
+	ts = kzalloc(sizeof(struct s3c_ts_info), GFP_KERNEL);
+	
+	input_dev = input_allocate_device();
+
+	if (!input_dev) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+	
+	ts->dev = input_dev;
+
+	ts->dev->evbit[0] = ts->dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+	ts->dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+
+	if (s3c_ts_cfg->resol_bit==12) {
+#if 0
+		input_set_abs_params(ts->dev, ABS_X, 0, 0xFFF, 0, 0);
+		input_set_abs_params(ts->dev, ABS_Y, 0, 0xFFF, 0, 0);
+#else
+		input_set_abs_params(ts->dev, ABS_X, 0, 800, 0, 0);
+		input_set_abs_params(ts->dev, ABS_Y, 0, 480, 0, 0);
+#endif
+	}
+	else {
+		input_set_abs_params(ts->dev, ABS_X, 0, 0x3FF, 0, 0);
+		input_set_abs_params(ts->dev, ABS_Y, 0, 0x3FF, 0, 0);
+	}
+
+	input_set_abs_params(ts->dev, ABS_PRESSURE, 0, 1, 0, 0);
+
+	sprintf(ts->phys, "input(ts)");
+
+	ts->dev->name = s3c_ts_name;
+	ts->dev->phys = ts->phys;
+	ts->dev->id.bustype = BUS_RS232;
+	ts->dev->id.vendor = 0xDEAD;
+	ts->dev->id.product = 0xBEEF;
+	ts->dev->id.version = S3C_TSVERSION;
+
+	ts->shift = s3c_ts_cfg->oversampling_shift;
+	ts->resol_bit = s3c_ts_cfg->resol_bit;
+	ts->s3c_adc_con = s3c_ts_cfg->s3c_adc_con;
+	
+	/* For IRQ_PENDUP */
+	ts_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (ts_irq == NULL) {
+		dev_err(dev, "no irq resource specified\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+	ret = request_irq(ts_irq->start, stylus_updown, IRQF_SAMPLE_RANDOM, "s3c_updown", ts);
+	if (ret != 0) {
+		dev_err(dev,"s3c_ts.c: Could not allocate ts IRQ_PENDN !\n");
+		ret = -EIO;
+		goto err_clk;
+	}
+
+	/* For IRQ_ADC */
+	ts_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (ts_irq == NULL) {
+		dev_err(dev, "no irq resource specified\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+	ret = request_irq(ts_irq->start, stylus_action, IRQF_SAMPLE_RANDOM, "s3c_action", ts);
+	if (ret != 0) {
+		dev_err(dev, "s3c_ts.c: Could not allocate ts IRQ_ADC !\n");
+		ret =  -EIO;
+		goto err_irq;
+	}
+
+	printk(KERN_INFO "%s got loaded successfully : %d bits\n", s3c_ts_name, s3c_ts_cfg->resol_bit);
+
+	/* All went ok, so register to the input system */
+	ret = input_register_device(ts->dev);
+	
+	if(ret) {
+		dev_err(dev, "s3c_ts.c: Could not register input device(touchscreen)!\n");
+		ret = -EIO;
+		goto fail;
+	}
+
+	return 0;
+
+fail:	input_free_device(input_dev);
+	kfree(ts);
+	
+err_irq:
+	free_irq(ts_irq->start, ts->dev);
+	free_irq(ts_irq->end, ts->dev);
+	
+err_clk:
+	clk_disable(ts_clock);
+	clk_put(ts_clock);
+	
+err_map:
+	iounmap(ts_base);
+
+err_req:
+	release_resource(ts_mem);
+	kfree(ts_mem);
+
+	return ret;
+}
+
+static int s3c_ts_remove(struct platform_device *dev)
+{
+	printk(KERN_INFO "s3c_ts_remove() of TS called !\n");
+
+	disable_irq(IRQ_ADC);
+	disable_irq(IRQ_PENDN);
+	
+	free_irq(IRQ_PENDN, ts->dev);
+	free_irq(IRQ_ADC, ts->dev);
+
+	if (ts_clock) {
+		clk_disable(ts_clock);
+		clk_put(ts_clock);
+		ts_clock = NULL;
+	}
+
+	input_unregister_device(ts->dev);
+	iounmap(ts_base);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static unsigned int adccon, adctsc, adcdly;
+
+static int s3c_ts_suspend(struct platform_device *dev, pm_message_t state)
+{
+	adccon = readl(ts_base+S3C_ADCCON);
+	adctsc = readl(ts_base+S3C_ADCTSC);
+	adcdly = readl(ts_base+S3C_ADCDLY);
+
+	disable_irq(IRQ_ADC);
+	disable_irq(IRQ_PENDN);
+	
+	clk_disable(ts_clock);
+
+	return 0;
+}
+
+static int s3c_ts_resume(struct platform_device *pdev)
+{
+	clk_enable(ts_clock);
+
+	writel(adccon, ts_base+S3C_ADCCON);
+	writel(adctsc, ts_base+S3C_ADCTSC);
+	writel(adcdly, ts_base+S3C_ADCDLY);
+	writel(WAIT4INT(0), ts_base+S3C_ADCTSC);
+
+	enable_irq(IRQ_ADC);
+	enable_irq(IRQ_PENDN);
+	return 0;
+}
+#else
+#define s3c_ts_suspend NULL
+#define s3c_ts_resume  NULL
+#endif
+
+static struct platform_driver s3c_ts_driver = {
+       .probe          = s3c_ts_probe,
+       .remove         = s3c_ts_remove,
+       .suspend        = s3c_ts_suspend,
+       .resume         = s3c_ts_resume,
+       .driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "s3c-ts",
+	},
+};
+
+static char banner[] __initdata = KERN_INFO "S3C Touchscreen driver, (c) 2008 Samsung Electronics\n";
+
+static int __init s3c_ts_init(void)
+{
+	printk(banner);
+	return platform_driver_register(&s3c_ts_driver);
+}
+
+static void __exit s3c_ts_exit(void)
+{
+	platform_driver_unregister(&s3c_ts_driver);
+}
+
+module_init(s3c_ts_init);
+module_exit(s3c_ts_exit);
+
+MODULE_AUTHOR("Samsung AP");
+MODULE_DESCRIPTION("S3C touchscreen driver");
+MODULE_LICENSE("GPL");
diff -urN android_2.6.29_org/drivers/input/touchscreen/smb380.c android_2.6.29/drivers/input/touchscreen/smb380.c
--- android_2.6.29_org/drivers/input/touchscreen/smb380.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/smb380.c	2007-08-07 18:05:10.000000000 +0900
@@ -0,0 +1,1189 @@
+/*  $Date: 2007/08/07 16:05:10 $
+ *  $Revision: 1.4 $
+ *  
+ */
+
+/*
+* Copyright (C) 2007 Bosch Sensortec GmbH
+*
+* SMB380 acceleration sensor API
+* 
+* Usage:	Application Programming Interface for SMB380 configuration and data read out
+*
+* Author:	Lars.Beseke@bosch-sensortec.com
+*
+* Disclaimer
+*
+* Common:
+* Bosch Sensortec products are developed for the consumer goods industry. They may only be used 
+* within the parameters of the respective valid product data sheet.  Bosch Sensortec products are 
+* provided with the express understanding that there is no warranty of fitness for a particular purpose. 
+* They are not fit for use in life-sustaining, safety or security sensitive systems or any system or device 
+* that may lead to bodily harm or property damage if the system or device malfunctions. In addition, 
+* Bosch Sensortec products are not fit for use in products which interact with motor vehicle systems.  
+* The resale and/or use of products are at the purchaser’s own risk and his own responsibility. The 
+* examination of fitness for the intended use is the sole responsibility of the Purchaser. 
+*
+* The purchaser shall indemnify Bosch Sensortec from all third party claims, including any claims for 
+* incidental, or consequential damages, arising from any product use not covered by the parameters of 
+* the respective valid product data sheet or not approved by Bosch Sensortec and reimburse Bosch 
+* Sensortec for all costs in connection with such claims.
+*
+* The purchaser must monitor the market for the purchased products, particularly with regard to 
+* product safety and inform Bosch Sensortec without delay of all security relevant incidents.
+*
+* Engineering Samples are marked with an asterisk (*) or (e). Samples may vary from the valid 
+* technical specifications of the product series. They are therefore not intended or fit for resale to third 
+* parties or for use in end products. Their sole purpose is internal client testing. The testing of an 
+* engineering sample may in no way replace the testing of a product series. Bosch Sensortec 
+* assumes no liability for the use of engineering samples. By accepting the engineering samples, the 
+* Purchaser agrees to indemnify Bosch Sensortec from all claims arising from the use of engineering 
+* samples.
+*
+* Special:
+* This software module (hereinafter called "Software") and any information on application-sheets 
+* (hereinafter called "Information") is provided free of charge for the sole purpose to support your 
+* application work. The Software and Information is subject to the following terms and conditions: 
+*
+* The Software is specifically designed for the exclusive use for Bosch Sensortec products by 
+* personnel who have special experience and training. Do not use this Software if you do not have the 
+* proper experience or training. 
+*
+* This Software package is provided `` as is `` and without any expressed or implied warranties, 
+* including without limitation, the implied warranties of merchantability and fitness for a particular 
+* purpose. 
+*
+* Bosch Sensortec and their representatives and agents deny any liability for the functional impairment 
+* of this Software in terms of fitness, performance and safety. Bosch Sensortec and their 
+* representatives and agents shall not be liable for any direct or indirect damages or injury, except as 
+* otherwise stipulated in mandatory applicable law.
+* 
+* The Information provided is believed to be accurate and reliable. Bosch Sensortec assumes no 
+* responsibility for the consequences of use of such Information nor for any infringement of patents or 
+* other rights of third parties which may result from its use. No license is granted by implication or 
+* otherwise under any patent or patent rights of Bosch. Specifications mentioned in the Information are 
+* subject to change without notice.
+*
+* It is not allowed to deliver the source code of the Software to any third party without permission of 
+* Bosch Sensortec.
+*/
+
+
+/*! \file smb380.c
+    \brief This file contains all function implementations for the SMB380 API
+    
+    Details.
+*/
+
+
+#include "smb380.h"
+
+
+smb380_t *p_smb380;				/**< pointer to SMB380 device structure  */
+
+
+/** API Initialization routine
+ \param *smb380 pointer to SMB380 structured type
+ \return result of communication routines 
+ */
+
+int smb380_init(smb380_t *smb380) 
+{
+	int comres=0;
+	unsigned char data;
+
+	p_smb380 = smb380;																			/* assign smb380 ptr */
+	p_smb380->dev_addr = SMB380_I2C_ADDR;										/* preset SM380 I2C_addr */
+	comres += p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, CHIP_ID__REG, &data, 1);	/* read Chip Id */
+	
+	p_smb380->chip_id = SMB380_GET_BITSLICE(data, CHIP_ID);						/* get bitslice */
+		
+	comres += p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ML_VERSION__REG, &data, 1); /* read Version reg */
+	p_smb380->ml_version = SMB380_GET_BITSLICE(data, ML_VERSION);				/* get ML Version */
+	p_smb380->al_version = SMB380_GET_BITSLICE(data, AL_VERSION);				/* get AL Version */
+
+	return comres;
+
+}
+
+/** Perform soft reset of SMB380 via bus command
+*/
+int smb380_soft_reset() 
+{
+	int comres;
+	unsigned char data=0;
+	if (p_smb380==0) 
+		return E_SMB_NULL_PTR;
+	data = SMB380_SET_BITSLICE(data, SOFT_RESET, 1);
+  comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, SOFT_RESET__REG, &data,1); 
+	return comres;
+}
+
+
+/** call SMB380s update image function
+	\return bus communication result
+*/
+int smb380_update_image() 
+{
+	int comres;
+	unsigned char data=0;
+	if (p_smb380==0) 
+		return E_SMB_NULL_PTR;
+	data = SMB380_SET_BITSLICE(data, UPDATE_IMAGE, 1);
+    comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, UPDATE_IMAGE__REG, &data,1); 
+	return comres;
+}
+
+
+/** copy image from image structure to SMB380 image memory
+   \param smb380Image Pointer to smb380regs_t
+   \return result of bus communication function
+*/
+int smb380_set_image (smb380regs_t *smb380Image) 
+{
+	int comres;
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+    comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, EE_W__REG,&data, 1);
+	data = SMB380_SET_BITSLICE(data, EE_W, SMB380_EE_W_ON);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, EE_W__REG, &data, 1);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, SMB380_IMAGE_BASE, (unsigned char*)smb380Image, SMB380_IMAGE_LEN);
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, EE_W__REG,&data, 1);
+	data = SMB380_SET_BITSLICE(data, EE_W, SMB380_EE_W_OFF);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, EE_W__REG, &data, 1);
+	return comres;
+}
+
+
+
+/** read out image from SMB380 and store it to smb380regs_t structure
+   \param smb380Image pointer to smb380regs_t 
+   \return result of bus communication function
+
+*/
+int smb380_get_image(smb380regs_t *smb380Image)
+{
+
+	int comres;
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+        comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, EE_W__REG,&data, 1);
+	data = SMB380_SET_BITSLICE(data, EE_W, SMB380_EE_W_ON);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, EE_W__REG, &data, 1);
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SMB380_IMAGE_BASE, (unsigned char *)smb380Image, SMB380_IMAGE_LEN);
+	data = SMB380_SET_BITSLICE(data, EE_W, SMB380_EE_W_OFF);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, EE_W__REG, &data, 1);
+	return comres;
+}
+
+/** read out offset data from 
+   \param xyz select axis x=0, y=1, z=2
+   \param *offset pointer to offset value (offset is in offset binary representation
+   \return result of bus communication function
+   \note use smb380_set_ee_w() function to enable access to offset registers 
+*/
+int smb380_get_offset(unsigned char xyz, unsigned short *offset) 
+{
+
+   int comres;
+   unsigned char data;
+   if (p_smb380==0)
+   		return E_SMB_NULL_PTR;
+   comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, (OFFSET_X_LSB__REG+xyz), &data, 1);
+   data = SMB380_GET_BITSLICE(data, OFFSET_X_LSB);
+   *offset = data;
+   comres += p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, (OFFSET_X_MSB__REG+xyz), &data, 1);
+   *offset |= (data<<2);
+   return comres;
+}
+
+
+/** write offset data to SMB380 image
+   \param xyz select axis x=0, y=1, z=2
+   \param offset value to write (offset is in offset binary representation
+   \return result of bus communication function
+   \note use smb380_set_ee_w() function to enable access to offset registers 
+*/
+int smb380_set_offset(unsigned char xyz, unsigned short offset) 
+{
+
+   int comres;
+   unsigned char data;
+   if (p_smb380==0)
+   		return E_SMB_NULL_PTR;
+   comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, (OFFSET_X_LSB__REG+xyz), &data, 1);
+   data = SMB380_SET_BITSLICE(data, OFFSET_X_LSB, offset);
+   comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, (OFFSET_X_LSB__REG+xyz), &data, 1);
+   data = (offset&0x3ff)>>2;
+   comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, (OFFSET_X_MSB__REG+xyz), &data, 1);
+   return comres;
+}
+
+
+/** write offset data to SMB380 image
+   \param xyz select axis x=0, y=1, z=2
+   \param offset value to write to eeprom(offset is in offset binary representation
+   \return result of bus communication function
+   \note use smb380_set_ee_w() function to enable access to offset registers in EEPROM space
+*/
+int smb380_set_offset_eeprom(unsigned char xyz, unsigned short offset) 
+{
+
+   int comres;
+   unsigned char data;
+   if (p_smb380==0)
+   		return E_SMB_NULL_PTR;   
+   comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, (OFFSET_X_LSB__REG+xyz), &data, 1);
+   data = SMB380_SET_BITSLICE(data, OFFSET_X_LSB, offset);
+   comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, (SMB380_EEP_OFFSET+OFFSET_X_LSB__REG + xyz), &data, 1);   
+   p_smb380->delay_msec(34);
+   data = (offset&0x3ff)>>2;
+   comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, (SMB380_EEP_OFFSET+ OFFSET_X_MSB__REG+xyz), &data, 1);
+   p_smb380->delay_msec(34);
+   return comres;
+}
+
+
+
+
+/** write offset data to SMB380 image
+   \param eew 0 = lock EEPROM 1 = unlock EEPROM 
+   \return result of bus communication function
+*/
+int smb380_set_ee_w(unsigned char eew)
+{
+    unsigned char data;
+	int comres;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+    comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, EE_W__REG,&data, 1);
+	data = SMB380_SET_BITSLICE(data, EE_W, eew);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, EE_W__REG, &data, 1);
+	return comres;
+}
+
+
+
+/** write byte to SMB380 EEPROM
+   \param addr address to write to (image addresses are automatically extended to EEPROM space)
+   \param data byte content to write 
+   \return result of bus communication function
+*/
+int smb380_write_ee(unsigned char addr, unsigned char data) 
+{	
+	int comres;
+	if (p_smb380==0) 			/* check pointers */
+		return E_SMB_NULL_PTR;
+    if (p_smb380->delay_msec == 0)
+	    return E_SMB_NULL_PTR;
+    comres = smb380_set_ee_w( SMB380_EE_W_ON );
+	addr|=0x20;   /* add eeprom address offset to image address if not applied */
+	comres += smb380_write_reg(addr, &data, 1 );
+	p_smb380->delay_msec( SMB380_EE_W_DELAY );
+	comres += smb380_set_ee_w( SMB380_EE_W_OFF);
+	return comres;
+}
+
+/**	start SMB380s integrated selftest function
+   \param st 1 = selftest0, 3 = selftest1 (see also)
+ 	 \return result of bus communication function
+ 	 
+ 	 \see SMB380_SELF_TEST0_ON
+ 	 \see SMB380_SELF_TEST1_ON
+ 
+ */
+int smb380_selftest(unsigned char st)
+{
+	int comres;
+	unsigned char data;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SELF_TEST__REG, &data, 1);
+	data = SMB380_SET_BITSLICE(data, SELF_TEST, st);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, SELF_TEST__REG, &data, 1);  
+	return comres;  
+
+}
+
+
+
+/**	set smb380s range 
+ \param range 
+ \return  result of bus communication function
+ 
+ \see SMB380_RANGE_2G		
+ \see SMB380_RANGE_4G			
+ \see SMB380_RANGE_8G			
+*/
+int smb380_set_range(char range) 
+{			
+   int comres = 0;
+   unsigned char data;
+
+   if (p_smb380==0)
+	    return E_SMB_NULL_PTR;
+
+   if (range<3) {	
+	 	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, RANGE__REG, &data, 1 );
+	 	data = SMB380_SET_BITSLICE(data, RANGE, range);		  	
+         comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, RANGE__REG, &data, 1);
+   }
+   return comres;
+
+}
+
+
+/* readout select range from SMB380 
+   \param *range pointer to range setting
+   \return result of bus communication function
+   \see SMB380_RANGE_2G, SMB380_RANGE_4G, SMB380_RANGE_8G		
+   \see smb380_set_range()
+*/
+int smb380_get_range(unsigned char *range) 
+{
+
+	int comres = 0;
+	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, RANGE__REG, range, 1 );
+
+	*range = SMB380_GET_BITSLICE(*range, RANGE);
+	
+	return comres;
+
+}
+
+
+
+/** set SMB380s operation mode
+   \param mode 0 = normal, 2 = sleep, 3 = auto wake up
+   \return result of bus communication function
+   \note Available constants see below
+   \see SMB380_MODE_NORMAL, SMB380_MODE_SLEEP, SMB380_MODE_WAKE_UP     
+	 \see smb380_get_mode()
+*/
+int smb380_set_mode(unsigned char mode) {
+	
+	int comres=0;
+	unsigned char data1, data2;
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	if (mode<4 || mode!=1) {
+		comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, WAKE_UP__REG, &data1, 1 );
+		data1  = SMB380_SET_BITSLICE(data1, WAKE_UP, mode);		  
+        comres += p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SLEEP__REG, &data2, 1 );
+		data2  = SMB380_SET_BITSLICE(data2, SLEEP, (mode>>1));
+    	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, WAKE_UP__REG, &data1, 1);
+	  	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, SLEEP__REG, &data2, 1);
+	  	p_smb380->mode = mode;
+	} 
+	return comres;
+	
+}
+
+
+
+/** get selected mode
+   \return used mode
+   \note this function returns the mode stored in \ref smb380_t structure
+   \see SMB380_MODE_NORMAL, SMB380_MODE_SLEEP, SMB380_MODE_WAKE_UP
+   \see smb380_set_mode()
+
+*/
+unsigned char smb380_get_mode(void) 
+{
+    if (p_smb380==0)
+    	return E_SMB_NULL_PTR;	
+		return p_smb380->mode;
+	
+}
+
+/** set SMB380 internal filter bandwidth
+   \param bw bandwidth (see bandwidth constants)
+   \return result of bus communication function
+   \see #define SMB380_BW_25HZ, SMB380_BW_50HZ, SMB380_BW_100HZ, SMB380_BW_190HZ, SMB380_BW_375HZ, SMB380_BW_750HZ, SMB380_BW_1500HZ
+   \see smb380_get_bandwidth()
+*/
+int smb380_set_bandwidth(char bw) 
+{
+	int comres = 0;
+	unsigned char data;
+
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	if (bw<8) {
+
+  	  comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, RANGE__REG, &data, 1 );
+	  data = SMB380_SET_BITSLICE(data, BANDWIDTH, bw);
+	  comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, RANGE__REG, &data, 1 );
+
+	}
+    return comres;
+
+
+}
+
+/** read selected bandwidth from SMB380 
+ \param *bw pointer to bandwidth return value
+ \return result of bus communication function
+ \see #define SMB380_BW_25HZ, SMB380_BW_50HZ, SMB380_BW_100HZ, SMB380_BW_190HZ, SMB380_BW_375HZ, SMB380_BW_750HZ, SMB380_BW_1500HZ
+ \see smb380_set_bandwidth()
+*/
+int smb380_get_bandwidth(unsigned char *bw) {
+	int comres = 1;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, BANDWIDTH__REG, bw, 1 );		
+
+	*bw = SMB380_GET_BITSLICE(*bw, BANDWIDTH);
+	
+	return comres;
+
+}
+
+/** set SMB380 auto wake up pause
+  \param wup wake_up_pause parameters
+	\return result of bus communication function
+	\see SMB380_WAKE_UP_PAUSE_20MS, SMB380_WAKE_UP_PAUSE_80MS, SMB380_WAKE_UP_PAUSE_320MS, SMB380_WAKE_UP_PAUSE_2560MS
+	\see smb380_get_wake_up_pause()
+*/
+
+int smb380_set_wake_up_pause(unsigned char wup)
+{
+	int comres=0;
+	unsigned char data;
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+
+	    comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, WAKE_UP_PAUSE__REG, &data, 1 );
+		data = SMB380_SET_BITSLICE(data, WAKE_UP_PAUSE, wup);
+		comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, WAKE_UP_PAUSE__REG, &data, 1 );
+	return comres;
+}
+
+/** read SMB380 auto wake up pause from image
+  \param *wup wake up pause read back pointer
+	\see SMB380_WAKE_UP_PAUSE_20MS, SMB380_WAKE_UP_PAUSE_80MS, SMB380_WAKE_UP_PAUSE_320MS, SMB380_WAKE_UP_PAUSE_2560MS
+	\see smb380_set_wake_up_pause()
+*/
+int smb380_get_wake_up_pause(unsigned char *wup)
+{
+    int comres = 1;
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, WAKE_UP_PAUSE__REG, &data,  1 );		
+	
+	*wup = SMB380_GET_BITSLICE(data, WAKE_UP_PAUSE);
+	
+	return comres;
+
+}
+
+
+/* Thresholds and Interrupt Configuration */
+
+
+/** set low-g interrupt threshold
+   \param th set the threshold
+   \note the threshold depends on configured range. A macro \ref SMB380_LG_THRES_IN_G() for range to register value conversion is available.
+   \see SMB380_LG_THRES_IN_G()   
+   \see smb380_get_low_g_threshold()
+*/
+int smb380_set_low_g_threshold(unsigned char th) 
+{
+
+	int comres;	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;		
+
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, LG_THRES__REG, &th, 1);
+	return comres;
+	
+}
+
+
+/** get low-g interrupt threshold
+   \param *th get the threshold  value from sensor image
+   \see smb380_set_low_g_threshold()
+*/
+int smb380_get_low_g_threshold(unsigned char *th)
+{
+
+	int comres=1;	
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;	
+
+		comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, LG_THRES__REG, th, 1);		
+
+	return comres;
+
+}
+
+
+/** set low-g interrupt countdown
+   \param cnt get the countdown value from sensor image
+   \see smb380_get_low_g_countdown()
+*/
+int smb380_set_low_g_countdown(unsigned char cnt)
+{
+	int comres=0;
+	unsigned char data;
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+  comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, COUNTER_LG__REG, &data, 1 );
+  data = SMB380_SET_BITSLICE(data, COUNTER_LG, cnt);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, COUNTER_LG__REG, &data, 1 );
+	return comres;
+}
+
+
+/** get low-g interrupt countdown
+   \param cnt get the countdown  value from sensor image
+   \see smb380_set_low_g_countdown()
+*/
+int smb380_get_low_g_countdown(unsigned char *cnt)
+{
+    int comres = 1;
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, COUNTER_LG__REG, &data,  1 );		
+	*cnt = SMB380_GET_BITSLICE(data, COUNTER_LG);
+	
+	return comres;
+}
+
+/** set high-g interrupt countdown
+   \param cnt get the countdown value from sensor image
+   \see smb380_get_high_g_countdown()
+*/
+int smb380_set_high_g_countdown(unsigned char cnt)
+{
+	int comres=1;
+	unsigned char data;
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+
+        comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, COUNTER_HG__REG, &data, 1 );
+	data = SMB380_SET_BITSLICE(data, COUNTER_HG, cnt);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, COUNTER_HG__REG, &data, 1 );
+	return comres;
+}
+
+/** get high-g interrupt countdown
+   \param cnt get the countdown  value from sensor image
+   \see smb380_set_high_g_countdown()
+*/
+int smb380_get_high_g_countdown(unsigned char *cnt)
+{
+    int comres = 0;
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, COUNTER_HG__REG, &data,  1 );		
+	
+	*cnt = SMB380_GET_BITSLICE(data, COUNTER_HG);
+	
+	return comres;
+
+}
+
+
+/** configure low-g duration value
+	\param dur low-g duration in miliseconds
+	\see smb380_get_low_g_duration(), smb380_get_high_g_duration(), smb380_set_high_g_duration()
+	
+*/
+int smb380_set_low_g_duration(unsigned char dur) 
+{
+	int comres=0;	
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	
+	
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, LG_DUR__REG, &dur, 1);
+
+	return comres;
+}
+
+
+
+
+/** read out low-g duration value from sensor image
+	\param dur low-g duration in miliseconds
+	\see smb380_set_low_g_duration(), smb380_get_high_g_duration(), smb380_set_high_g_duration()
+	
+*/
+int smb380_get_low_g_duration(unsigned char *dur) {
+	
+	int comres=0;	
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, LG_DUR__REG, dur, 1);				  
+	return comres;
+
+}
+
+
+
+
+/** set low-g interrupt threshold
+   \param th set the threshold
+   \note the threshold depends on configured range. A macro \ref SMB380_HG_THRES_IN_G() for range to register value conversion is available.
+   \see SMB380_HG_THRES_IN_G()   
+   \see smb380_get_high_g_threshold()
+*/
+int smb380_set_high_g_threshold(unsigned char th) 
+{
+
+	int comres=0;	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, HG_THRES__REG, &th, 1);
+	return comres;
+	
+}
+
+/** get high-g interrupt threshold
+   \param *th get the threshold  value from sensor image
+   \see smb380_set_high_g_threshold()
+*/
+int smb380_get_high_g_threshold(unsigned char *th)
+{
+
+	int comres=0;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, HG_THRES__REG, th, 1);		
+
+	return comres;
+
+}
+
+
+
+/** configure high-g duration value
+	\param dur high-g duration in miliseconds
+	\see  smb380_get_high_g_duration(), smb380_set_low_g_duration(), smb380_get_low_g_duration()
+	
+*/
+int smb380_set_high_g_duration(unsigned char dur) 
+{
+	int comres=0;	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, HG_DUR__REG, &dur, 1);
+	return comres;
+}
+
+
+/** read out high-g duration value from sensor image
+	\param dur high-g duration in miliseconds
+	\see  smb380_set_high_g_duration(), smb380_get_low_g_duration(), smb380_set_low_g_duration(),
+	
+*/
+int smb380_get_high_g_duration(unsigned char *dur) {	
+	
+	int comres=0;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+			
+        comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, HG_DUR__REG, dur, 1);		
+
+	return comres;
+
+}
+
+
+
+
+/**  set threshold value for any_motion feature
+		\param th set the threshold a macro \ref SMB380_ANY_MOTION_THRES_IN_G()  is available for that
+		\see SMB380_ANY_MOTION_THRES_IN_G()
+*/
+int smb380_set_any_motion_threshold(unsigned char th) 
+{
+	int comres=0;	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, ANY_MOTION_THRES__REG, &th, 1);
+
+	return comres;
+}
+
+
+/**  get threshold value for any_motion feature
+		\param *th read back any_motion threshold from image register 
+		\see SMB380_ANY_MOTION_THRES_IN_G()
+*/
+int smb380_get_any_motion_threshold(unsigned char *th)
+{
+
+	int comres=0;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ANY_MOTION_THRES__REG, th, 1);		
+
+	return comres;
+
+}
+
+/**  set counter value for any_motion feature 
+		\param amc set the counter value, constants are available for that
+		\see SMB380_ANY_MOTION_DUR_1, SMB380_ANY_MOTION_DUR_3, SMB380_ANY_MOTION_DUR_5, SMB380_ANY_MOTION_DUR_7
+*/
+int smb380_set_any_motion_count(unsigned char amc)
+{
+	int comres=0;	
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+ 	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ANY_MOTION_DUR__REG, &data, 1 );
+	data = SMB380_SET_BITSLICE(data, ANY_MOTION_DUR, amc);
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, ANY_MOTION_DUR__REG, &data, 1 );
+	return comres;
+}
+
+
+/**  get counter value for any_motion feature from image register
+		\param *amc readback pointer for counter value
+		\see SMB380_ANY_MOTION_DUR_1, SMB380_ANY_MOTION_DUR_3, SMB380_ANY_MOTION_DUR_5, SMB380_ANY_MOTION_DUR_7
+*/
+int smb380_get_any_motion_count(unsigned char *amc)
+{
+    int comres = 0;
+	unsigned char data;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ANY_MOTION_DUR__REG, &data,  1 );		
+	
+	*amc = SMB380_GET_BITSLICE(data, ANY_MOTION_DUR);
+	return comres;
+
+}
+
+
+
+
+/** set the interrupt mask for SMB380's interrupt features in one mask
+	\param mask input for interrupt mask
+	\see SMB380_INT_ALERT, SMB380_INT_ANY_MOTION, SMB380_INT_EN_ADV_INT, SMB380_INT_NEW_DATA, SMB380_INT_LATCH, SMB380_INT_HG, SMB380_INT_LG
+*/
+int smb380_set_interrupt_mask(unsigned char mask) 
+{
+	int comres=0;
+	unsigned char data[4];
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	data[0] = mask & SMB380_CONF1_INT_MSK;
+	data[2] = ((mask<<1) & SMB380_CONF2_INT_MSK);		
+
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SMB380_CONF1_REG, &data[1], 1);
+	comres += p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SMB380_CONF2_REG, &data[3], 1);		
+	data[1] &= (~SMB380_CONF1_INT_MSK);
+	data[1] |= data[0];
+	data[3] &=(~(SMB380_CONF2_INT_MSK));
+	data[3] |= data[2];
+
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, SMB380_CONF1_REG, &data[1], 1);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, SMB380_CONF2_REG, &data[3], 1);
+
+	return comres;	
+}
+
+/** get the current interrupt mask settings from SMB380 image registers
+	\param *mask return variable pointer for interrupt mask
+	\see SMB380_INT_ALERT, SMB380_INT_ANY_MOTION, SMB380_INT_EN_ADV_INT, SMB380_INT_NEW_DATA, SMB380_INT_LATCH, SMB380_INT_HG, SMB380_INT_LG
+*/
+int smb380_get_interrupt_mask(unsigned char *mask) 
+{
+	int comres=0;
+	unsigned char data;
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SMB380_CONF1_REG, &data,1);
+	*mask = data & SMB380_CONF1_INT_MSK;
+	p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SMB380_CONF2_REG, &data,1);
+	*mask = *mask | ((data & SMB380_CONF2_INT_MSK)>>1);
+
+	return comres;
+}
+
+
+/** resets the SMB380 interrupt status 
+		\note this feature can be used to reset a latched interrupt
+
+*/
+int smb380_reset_interrupt(void) 
+{	
+	int comres=0;
+	unsigned char data=(1<<RESET_INT__POS);	
+	
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, RESET_INT__REG, &data, 1);
+	return comres;
+
+}
+
+
+
+
+
+/* Data Readout */
+
+/** X-axis acceleration data readout 
+	\param *a_x pointer for 16 bit 2's complement data output (LSB aligned)
+*/
+int smb380_read_accel_x(short *a_x) 
+{
+	int comres;
+	unsigned char data[2];
+	
+	
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ACC_X_LSB__REG, data, 2);
+	*a_x = SMB380_GET_BITSLICE(data[0],ACC_X_LSB) | SMB380_GET_BITSLICE(data[1],ACC_X_MSB)<<ACC_X_LSB__LEN;
+	*a_x = *a_x << (sizeof(short)*8-(ACC_X_LSB__LEN+ACC_X_MSB__LEN));
+	*a_x = *a_x >> (sizeof(short)*8-(ACC_X_LSB__LEN+ACC_X_MSB__LEN));
+	return comres;
+	
+}
+
+
+
+/** Y-axis acceleration data readout 
+	\param *a_y pointer for 16 bit 2's complement data output (LSB aligned)
+*/
+int smb380_read_accel_y(short *a_y) 
+{
+	int comres;
+	unsigned char data[2];	
+
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ACC_Y_LSB__REG, data, 2);
+	*a_y = SMB380_GET_BITSLICE(data[0],ACC_Y_LSB) | SMB380_GET_BITSLICE(data[1],ACC_Y_MSB)<<ACC_Y_LSB__LEN;
+	*a_y = *a_y << (sizeof(short)*8-(ACC_Y_LSB__LEN+ACC_Y_MSB__LEN));
+	*a_y = *a_y >> (sizeof(short)*8-(ACC_Y_LSB__LEN+ACC_Y_MSB__LEN));
+	return comres;
+}
+
+
+/** Z-axis acceleration data readout 
+	\param *a_z pointer for 16 bit 2's complement data output (LSB aligned)
+*/
+int smb380_read_accel_z(short *a_z)
+{
+	int comres;
+	unsigned char data[2];	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ACC_Z_LSB__REG, data, 2);
+	*a_z = SMB380_GET_BITSLICE(data[0],ACC_Z_LSB) | SMB380_GET_BITSLICE(data[1],ACC_Z_MSB)<<ACC_Z_LSB__LEN;
+	*a_z = *a_z << (sizeof(short)*8-(ACC_Z_LSB__LEN+ACC_Z_MSB__LEN));
+	*a_z = *a_z >> (sizeof(short)*8-(ACC_Z_LSB__LEN+ACC_Z_MSB__LEN));
+	return comres;
+}
+
+
+/** 8 bit temperature data readout 
+	\param *temp pointer for 8 bit temperature output (offset binary)
+	\note: an output of 0 equals -30°C, 1 LSB equals 0.5°C
+*/
+int smb380_read_temperature(unsigned char * temp) 
+{
+	int comres;	
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, TEMPERATURE__REG, temp, 1);
+	return comres;
+
+}
+
+
+/** X,Y and Z-axis acceleration data readout 
+	\param *acc pointer to \ref smb380acc_t structure for x,y,z data readout
+	\note data will be read by multi-byte protocol into a 6 byte structure 
+*/
+int smb380_read_accel_xyz(smb380acc_t * acc)
+{
+	int comres;
+	unsigned char data[6];
+
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ACC_X_LSB__REG, &data[0],6);
+	
+	acc->x = SMB380_GET_BITSLICE(data[0],ACC_X_LSB) | (SMB380_GET_BITSLICE(data[1],ACC_X_MSB)<<ACC_X_LSB__LEN);
+	acc->x = acc->x << (sizeof(short)*8-(ACC_X_LSB__LEN+ACC_X_MSB__LEN));
+	acc->x = acc->x >> (sizeof(short)*8-(ACC_X_LSB__LEN+ACC_X_MSB__LEN));
+
+	acc->y = SMB380_GET_BITSLICE(data[2],ACC_Y_LSB) | (SMB380_GET_BITSLICE(data[3],ACC_Y_MSB)<<ACC_Y_LSB__LEN);
+	acc->y = acc->y << (sizeof(short)*8-(ACC_Y_LSB__LEN + ACC_Y_MSB__LEN));
+	acc->y = acc->y >> (sizeof(short)*8-(ACC_Y_LSB__LEN + ACC_Y_MSB__LEN));
+	
+	
+	acc->z = SMB380_GET_BITSLICE(data[4],ACC_Z_LSB); 
+	acc->z |= (SMB380_GET_BITSLICE(data[5],ACC_Z_MSB)<<ACC_Z_LSB__LEN);
+	acc->z = acc->z << (sizeof(short)*8-(ACC_Z_LSB__LEN+ACC_Z_MSB__LEN));
+	acc->z = acc->z >> (sizeof(short)*8-(ACC_Z_LSB__LEN+ACC_Z_MSB__LEN));
+	
+	return comres;
+	
+}
+
+
+
+/** check current interrupt status from interrupt status register in SMB380 image register
+	\param *ist pointer to interrupt status byte
+	\see SMB380_INT_STATUS_HG, SMB380_INT_STATUS_LG, SMB380_INT_STATUS_HG_LATCHED, SMB380_INT_STATUS_LG_LATCHED, SMB380_INT_STATUS_ALERT, SMB380_INT_STATUS_ST_RESULT
+*/
+int smb380_get_interrupt_status(unsigned char * ist) 
+{
+
+	int comres=0;	
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, SMB380_STATUS_REG, ist, 1);
+	return comres;
+}
+
+/** enable/ disable low-g interrupt feature
+		\param onoff enable=1, disable=0
+*/
+
+int smb380_set_low_g_int(unsigned char onoff) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ENABLE_LG__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, ENABLE_LG, onoff);
+	
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, ENABLE_LG__REG, &data, 1);
+	
+	return comres;
+
+}
+
+/** enable/ disable high-g interrupt feature
+		\param onoff enable=1, disable=0
+*/
+
+int smb380_set_high_g_int(unsigned char onoff) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ENABLE_HG__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, ENABLE_HG, onoff);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, ENABLE_HG__REG, &data, 1);
+	
+	return comres;
+
+}
+
+
+
+/** enable/ disable any_motion interrupt feature
+		\param onoff enable=1, disable=0
+		\note for any_motion interrupt feature usage see also \ref smb380_set_advanced_int()
+*/
+int smb380_set_any_motion_int(unsigned char onoff) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, EN_ANY_MOTION__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, EN_ANY_MOTION, onoff);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, EN_ANY_MOTION__REG, &data, 1);
+	
+	return comres;
+
+}
+
+/** enable/ disable alert-int interrupt feature
+		\param onoff enable=1, disable=0
+		\note for any_motion interrupt feature usage see also \ref smb380_set_advanced_int()
+*/
+int smb380_set_alert_int(unsigned char onoff) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ALERT__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, ALERT, onoff);
+
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, ALERT__REG, &data, 1);
+	
+	return comres;
+
+}
+
+
+/** enable/ disable advanced interrupt feature
+		\param onoff enable=1, disable=0
+		\see smb380_set_any_motion_int()
+		\see smb380_set_alert_int()
+*/
+int smb380_set_advanced_int(unsigned char onoff) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, ENABLE_ADV_INT__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, EN_ANY_MOTION, onoff);
+
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, ENABLE_ADV_INT__REG, &data, 1);
+	
+	return comres;
+
+}
+
+/** enable/disable latched interrupt for all interrupt feature (global option)
+	\param latched (=1 for latched interrupts), (=0 for unlatched interrupts) 
+*/
+
+int smb380_latch_int(unsigned char latched) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, LATCH_INT__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, LATCH_INT, latched);
+
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, LATCH_INT__REG, &data, 1);
+	
+	return comres;
+
+}
+
+
+
+/** enable/ disable new data interrupt feature
+		\param onoff enable=1, disable=0
+*/
+
+int smb380_set_new_data_int(unsigned char onoff) {
+	int comres;
+	unsigned char data;
+	if(p_smb380==0) 
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, NEW_DATA_INT__REG, &data, 1);				
+	data = SMB380_SET_BITSLICE(data, NEW_DATA_INT, onoff);
+	comres += p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, NEW_DATA_INT__REG, &data, 1);
+	
+	return comres;
+
+}
+
+
+
+/* MISC functions */
+
+
+/** calls the linked wait function
+
+		\param msec amount of mili seconds to pause
+		\return number of mili seconds waited
+*/
+
+int smb380_pause(int msec) 
+{
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+	else
+	  p_smb380->delay_msec(msec);	
+	return msec;
+
+}
+
+
+/** read function for raw register access
+
+		\param addr register address
+		\param *data pointer to data array for register read back
+		\param len number of bytes to be read starting from addr
+	
+*/
+
+int smb380_read_reg(unsigned char addr, unsigned char *data, unsigned char len)
+{
+
+	int comres;
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_READ_FUNC(p_smb380->dev_addr, addr, data, len);
+	return comres;
+
+}
+
+
+/** write function for raw register access
+		\param addr register address
+		\param *data pointer to data array for register write
+		\param len number of bytes to be written starting from addr	
+*/
+int smb380_write_reg(unsigned char addr, unsigned char *data, unsigned char len) 
+{
+
+	int comres;
+
+	if (p_smb380==0)
+		return E_SMB_NULL_PTR;
+
+	comres = p_smb380->SMB380_BUS_WRITE_FUNC(p_smb380->dev_addr, addr, data, len);
+
+	return comres;
+
+}
+
diff -urN android_2.6.29_org/drivers/input/touchscreen/smb380.h android_2.6.29/drivers/input/touchscreen/smb380.h
--- android_2.6.29_org/drivers/input/touchscreen/smb380.h	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/input/touchscreen/smb380.h	2007-08-07 18:18:54.000000000 +0900
@@ -0,0 +1,1070 @@
+/*  $Date: 2007/08/07 16:04:54 $
+ *  $Revision: 1.4 $
+ *
+ */
+
+
+/** \mainpage SMB380 Acceleration Sensor API
+ * Copyright (C) 2007 Bosch Sensortec GmbH
+ *  \section intro_sec Introduction
+ * SMB380 3-axis digital Accelerometer Programming Interface
+ * The SMB380 API enables quick access to Bosch Sensortec's 3-Axis digital accelerometer.
+ * The only mandatory steps are: 
+ *
+ * 1. linking the target application's communication functions to the API (\ref SMB380_WR_FUNC_PTR, \ref SMB380_RD_FUNC_PTR)
+ *
+ * 2. calling the smb380_init() routine, which initializes all necessary data structures for using all functions
+ *
+ * Author:	Lars.Beseke@bosch-sensortec.com
+ *
+ * 
+ * \section disclaimer_sec Disclaimer
+ *
+ *
+ *
+ * Common:
+ * Bosch Sensortec products are developed for the consumer goods industry. They may only be used 
+ * within the parameters of the respective valid product data sheet.  Bosch Sensortec products are 
+ * provided with the express understanding that there is no warranty of fitness for a particular purpose. 
+ * They are not fit for use in life-sustaining, safety or security sensitive systems or any system or device 
+ * that may lead to bodily harm or property damage if the system or device malfunctions. In addition, 
+ * Bosch Sensortec products are not fit for use in products which interact with motor vehicle systems.  
+ * The resale and/or use of products are at the purchaser’s own risk and his own responsibility. The 
+ * examination of fitness for the intended use is the sole responsibility of the Purchaser. 
+ *
+ * The purchaser shall indemnify Bosch Sensortec from all third party claims, including any claims for 
+ * incidental, or consequential damages, arising from any product use not covered by the parameters of 
+ * the respective valid product data sheet or not approved by Bosch Sensortec and reimburse Bosch 
+ * Sensortec for all costs in connection with such claims.
+ *
+ * The purchaser must monitor the market for the purchased products, particularly with regard to 
+ * product safety and inform Bosch Sensortec without delay of all security relevant incidents.
+ *
+ * Engineering Samples are marked with an asterisk (*) or (e). Samples may vary from the valid 
+ * technical specifications of the product series. They are therefore not intended or fit for resale to third 
+ * parties or for use in end products. Their sole purpose is internal client testing. The testing of an 
+ * engineering sample may in no way replace the testing of a product series. Bosch Sensortec 
+ * assumes no liability for the use of engineering samples. By accepting the engineering samples, the 
+ * Purchaser agrees to indemnify Bosch Sensortec from all claims arising from the use of engineering 
+ * samples.
+ *
+ * Special:
+ * This software module (hereinafter called "Software") and any information on application-sheets 
+ * (hereinafter called "Information") is provided free of charge for the sole purpose to support your 
+ * application work. The Software and Information is subject to the following terms and conditions: 
+ *
+ * The Software is specifically designed for the exclusive use for Bosch Sensortec products by 
+ * personnel who have special experience and training. Do not use this Software if you do not have the 
+ * proper experience or training. 
+ *
+ * This Software package is provided `` as is `` and without any expressed or implied warranties, 
+ * including without limitation, the implied warranties of merchantability and fitness for a particular 
+ * purpose. 
+ *
+ * Bosch Sensortec and their representatives and agents deny any liability for the functional impairment 
+ * of this Software in terms of fitness, performance and safety. Bosch Sensortec and their 
+ * representatives and agents shall not be liable for any direct or indirect damages or injury, except as 
+ * otherwise stipulated in mandatory applicable law.
+ * 
+ * The Information provided is believed to be accurate and reliable. Bosch Sensortec assumes no 
+ * responsibility for the consequences of use of such Information nor for any infringement of patents or 
+ * other rights of third parties which may result from its use. No license is granted by implication or 
+ * otherwise under any patent or patent rights of Bosch. Specifications mentioned in the Information are 
+ * subject to change without notice.
+ *
+ * It is not allowed to deliver the source code of the Software to any third party without permission of 
+ * Bosch Sensortec.
+ */
+
+ /** \file smb380.h
+    \brief Header file for all #define constants and function prototypes
+  
+    
+*/
+
+
+
+#ifndef __SMB380_H__
+#define __SMB380_H__
+
+
+
+/* SMB380 Macro for read and write commincation */
+
+
+/**
+   define for used read and write macros 
+*/
+
+
+/** Define the calling convention of YOUR bus communication routine.
+	\note This includes types of parameters. This example shows the configuration for an SPI bus link.
+
+	If your communication function looks like this:
+
+	write_my_bus_xy(unsigned char device_addr, unsigned char register_addr, unsigned char * data, unsigned char length);
+
+	The SMB380_WR_FUNC_PTR would equal:
+
+    #define	SMB380_WR_FUNC_PTR char (* bus_write)(unsigned char, unsigned char, unsigned char *, unsigned char)
+	
+	Parameters can be mixed as needed refer to the \ref SMB380_BUS_WRITE_FUNC  macro.
+	
+
+*/
+#define SMB380_WR_FUNC_PTR char (* bus_write)(unsigned char, unsigned char *, unsigned char)
+
+
+
+/** link makro between API function calls and bus write function
+	\note The bus write function can change since this is a system dependant issue.
+
+	If the bus_write parameter calling order is like: reg_addr, reg_data, wr_len it would be as it is here.
+
+	If the parameters are differently ordered or your communication function like I2C need to know the device address, 
+	you can change this macro accordingly.
+
+
+	define SMB380_BUS_WRITE_FUNC(dev_addr, reg_addr, reg_data, wr_len)\
+           bus_write(dev_addr, reg_addr, reg_data, wr_len)
+
+    This macro lets all API functions call YOUR communication routine in a way that equals your definition in the \ref SMB380_WR_FUNC_PTR definition.
+
+
+	      
+*/
+#define SMB380_BUS_WRITE_FUNC(dev_addr, reg_addr, reg_data, wr_len)\
+           bus_write(reg_addr, reg_data, wr_len)
+
+
+/** Define the calling convention of YOUR bus communication routine.
+	\note This includes types of parameters. This example shows the configuration for an SPI bus link.
+
+	If your communication function looks like this:
+
+	read_my_bus_xy(unsigned char device_addr, unsigned char register_addr, unsigned char * data, unsigned char length);
+
+	The SMB380_RD_FUNC_PTR would equal:
+
+    #define	SMB380_RD_FUNC_PTR char (* bus_read)(unsigned char, unsigned char, unsigned char *, unsigned char)
+	
+	Parameters can be mixed as needed refer to the \ref SMB380_BUS_READ_FUNC  macro.
+	
+
+*/
+
+#define SMB380_SPI_RD_MASK 0x80   /* for spi read transactions on SPI the MSB has to be set */
+#define SMB380_RD_FUNC_PTR char (* bus_read)( unsigned char, unsigned char *, unsigned char)
+
+
+/** link makro between API function calls and bus read function
+	\note The bus write function can change since this is a system dependant issue.
+
+	If the bus_read parameter calling order is like: reg_addr, reg_data, wr_len it would be as it is here.
+
+	If the parameters are differently ordered or your communication function like I2C need to know the device address, 
+	you can change this macro accordingly.
+
+
+	define SMB380_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, wr_len)\
+           bus_read(dev_addr, reg_addr, reg_data, wr_len)
+
+    This macro lets all API functions call YOUR communication routine in a way that equals your definition in the \ref SMB380_WR_FUNC_PTR definition.
+
+	\note: this macro also includes the "MSB='1'" for reading SMB380 addresses. 
+      
+*/
+#define SMB380_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, r_len)\
+           bus_read(reg_addr | SMB380_SPI_RD_MASK, reg_data, r_len)
+
+
+
+
+
+
+
+/** SMB380 I2C Address
+*/
+
+#define SMB380_I2C_ADDR		0x38
+
+
+/*
+	SMB380 API error codes
+*/
+
+#define E_SMB_NULL_PTR		(char)-127
+#define E_COMM_RES		    (char)-1
+#define E_OUT_OF_RANGE		(char)-2
+
+
+/* 
+ *	
+ *	register definitions 	
+ *
+ */
+
+
+#define SMB380_EEP_OFFSET   0x20
+#define SMB380_IMAGE_BASE	0x0b
+#define SMB380_IMAGE_LEN	19
+
+#define CHIP_ID_REG			0x00
+#define VERSION_REG			0x01
+#define X_AXIS_LSB_REG		0x02
+#define X_AXIS_MSB_REG		0x03
+#define Y_AXIS_LSB_REG		0x04
+#define Y_AXIS_MSB_REG		0x05
+#define Z_AXIS_LSB_REG		0x06
+#define Z_AXIS_MSB_REG		0x07
+#define TEMP_RD_REG			0x08
+#define SMB380_STATUS_REG	0x09
+#define SMB380_CTRL_REG		0x0a
+#define SMB380_CONF1_REG	0x0b
+#define LG_THRESHOLD_REG	0x0c
+#define LG_DURATION_REG		0x0d
+#define HG_THRESHOLD_REG	0x0e
+#define HG_DURATION_REG		0x0f
+#define MOTION_THRS_REG		0x10
+#define HYSTERESIS_REG		0x11
+#define CUSTOMER1_REG		0x12
+#define CUSTOMER2_REG		0x13
+#define RANGE_BWIDTH_REG	0x14
+#define SMB380_CONF2_REG	0x15
+
+#define OFFS_GAIN_X_REG		0x16
+#define OFFS_GAIN_Y_REG		0x17
+#define OFFS_GAIN_Z_REG		0x18
+#define OFFS_GAIN_T_REG		0x19
+#define OFFSET_X_REG		0x1a
+#define OFFSET_Y_REG		0x1b
+#define OFFSET_Z_REG		0x1c
+#define OFFSET_T_REG		0x1d
+
+
+/* register write and read delays */
+
+#define MDELAY_DATA_TYPE	unsigned int
+#define SMB380_EE_W_DELAY 28	/* delay after EEP write is 28 msec */
+
+
+
+/** SMB380 acceleration data 
+	\brief Structure containing acceleration values for x,y and z-axis in signed short
+
+*/
+
+typedef struct  {
+		short x, /**< holds x-axis acceleration data sign extended. Range -512 to 511. */
+			  y, /**< holds y-axis acceleration data sign extended. Range -512 to 511. */
+			  z; /**< holds z-axis acceleration data sign extended. Range -512 to 511. */
+} smb380acc_t;
+
+
+/** SMB380 image registers data structure
+	\brief Register type that contains all SMB380 image registers from address 0x0b to 0x15
+	This structure can hold the complete image data of SMB380
+
+*/
+typedef struct  {
+		unsigned char	
+		smb380_conf1 ,  /**<  image address 0x0b: interrupt enable bits, low-g settings */
+		lg_threshold,	/**<  image address 0x0c: low-g threshold, depends on selected g-range */
+		lg_duration,	/**<  image address 0x0d: low-g duration in ms */
+		hg_threshold,	/**<  image address 0x0e: high-g threshold, depends on selected g-range */
+		hg_duration,	/**<  image address 0x0f: high-g duration in ms */
+		motion_thrs,	/**<  image address 0x10: any motion threshold */
+		hysteresis,		/**<  image address 0x11: low-g and high-g hysteresis register */
+		customer1,		/**<  image address 0x12: customer reserved register 1 */
+		customer2,		/**<  image address 0x13: customer reserved register 2  */
+		range_bwidth,	/**<  image address 0x14: range and bandwidth selection register */
+		smb380_conf2,	/**<  image address 0x15: spi4, latched interrupt, auto-wake-up configuration */
+		offs_gain_x,	/**<  image address 0x16: offset_x LSB and x-axis gain settings */
+		offs_gain_y,	/**<  image address 0x17: offset_y LSB and y-axis gain settings */
+		offs_gain_z,	/**<  image address 0x18: offset_z LSB and z-axis gain settings */
+		offs_gain_t,	/**<  image address 0x19: offset_t LSB and temperature gain settings */
+		offset_x,		/**<  image address 0x1a: offset_x calibration MSB register */
+		offset_y,		/**<  image address 0x1b: offset_y calibration MSB register */ 
+		offset_z,		/**<  image address 0x1c: offset_z calibration MSB register */ 
+		offset_t;		/**<  image address 0x1d: temperature calibration MSB register */ 
+} smb380regs_t;
+
+
+/** smb380 typedef structure
+	\brief This structure holds all relevant information about SMB380 and links communication to the 
+*/
+
+typedef struct {	
+	smb380regs_t * image;	/**< pointer to smb380regs_t structure not mandatory */
+	unsigned char mode;		/**< save current SMB380 operation mode */
+	unsigned char chip_id,	/**< save SMB380's chip id which has to be 0x02 after calling smb380_init() */
+				  ml_version, /**< holds the SMB380 ML_version number */	
+				  al_version; /**< holds the SMB380 AL_version number */
+	unsigned char dev_addr;   /**< initializes SMB380's I2C device address 0x38 */
+	unsigned char int_mask;	  /**< stores the current SMB380 API generated interrupt mask */
+	SMB380_WR_FUNC_PTR;		  /**< function pointer to the SPI/I2C write function */
+	SMB380_RD_FUNC_PTR;		  /**< function pointer to the SPI/I2C read function */
+	void (*delay_msec)( MDELAY_DATA_TYPE ); /**< function pointer to a pause in mili seconds function */
+} smb380_t;
+
+
+
+
+	
+/* 
+ *	
+ *	bit slice positions in registers
+ *
+ */
+
+/** \cond BITSLICE */
+
+#define CHIP_ID__POS		0
+#define CHIP_ID__MSK		0x07
+#define CHIP_ID__LEN		3
+#define CHIP_ID__REG		CHIP_ID_REG
+
+
+#define ML_VERSION__POS		0
+#define ML_VERSION__LEN		4
+#define ML_VERSION__MSK		0x0F
+#define ML_VERSION__REG		VERSION_REG
+
+
+
+#define AL_VERSION__POS  	4
+#define AL_VERSION__LEN  	4
+#define AL_VERSION__MSK		0xF0
+#define AL_VERSION__REG		VERSION_REG
+
+
+/* DATA REGISTERS */
+
+
+#define NEW_DATA_X__POS  	0
+#define NEW_DATA_X__LEN  	1
+#define NEW_DATA_X__MSK  	0x01
+#define NEW_DATA_X__REG		X_AXIS_LSB_REG
+
+#define ACC_X_LSB__POS   	6
+#define ACC_X_LSB__LEN   	2
+#define ACC_X_LSB__MSK		0xC0
+#define ACC_X_LSB__REG		X_AXIS_LSB_REG
+
+#define ACC_X_MSB__POS   	0
+#define ACC_X_MSB__LEN   	8
+#define ACC_X_MSB__MSK		0xFF
+#define ACC_X_MSB__REG		X_AXIS_MSB_REG
+
+#define NEW_DATA_Y__POS  	0
+#define NEW_DATA_Y__LEN  	1
+#define NEW_DATA_Y__MSK  	0x01
+#define NEW_DATA_Y__REG		Y_AXIS_LSB_REG
+
+#define ACC_Y_LSB__POS   	6
+#define ACC_Y_LSB__LEN   	2
+#define ACC_Y_LSB__MSK   	0xC0
+#define ACC_Y_LSB__REG		Y_AXIS_LSB_REG
+
+#define ACC_Y_MSB__POS   	0
+#define ACC_Y_MSB__LEN   	8
+#define ACC_Y_MSB__MSK   	0xFF
+#define ACC_Y_MSB__REG		Y_AXIS_MSB_REG
+
+#define NEW_DATA_Z__POS  	0
+#define NEW_DATA_Z__LEN  	1
+#define NEW_DATA_Z__MSK		0x01
+#define NEW_DATA_Z__REG		Z_AXIS_LSB_REG
+
+#define ACC_Z_LSB__POS   	6
+#define ACC_Z_LSB__LEN   	2
+#define ACC_Z_LSB__MSK		0xC0
+#define ACC_Z_LSB__REG		Z_AXIS_LSB_REG
+
+#define ACC_Z_MSB__POS   	0
+#define ACC_Z_MSB__LEN   	8
+#define ACC_Z_MSB__MSK		0xFF
+#define ACC_Z_MSB__REG		Z_AXIS_MSB_REG
+
+#define TEMPERATURE__POS 	0
+#define TEMPERATURE__LEN 	8
+#define TEMPERATURE__MSK 	0xFF
+#define TEMPERATURE__REG	TEMP_RD_REG
+
+
+
+
+/* STATUS BITS */
+
+#define STATUS_HG__POS		0
+#define STATUS_HG__LEN		1
+#define STATUS_HG__MSK		0x01
+#define STATUS_HG__REG		SMB380_STATUS_REG
+
+#define STATUS_LG__POS		1
+#define STATUS_LG__LEN		1
+#define STATUS_LG__MSK		0x02
+#define STATUS_LG__REG		SMB380_STATUS_REG
+
+#define HG_LATCHED__POS  	2
+#define HG_LATCHED__LEN  	1
+#define HG_LATCHED__MSK		0x04
+#define HG_LATCHED__REG		SMB380_STATUS_REG
+
+#define LG_LATCHED__POS		3
+#define LG_LATCHED__LEN		1
+#define LG_LATCHED__MSK		8
+#define LG_LATCHED__REG		SMB380_STATUS_REG
+
+#define ALERT_PHASE__POS	4
+#define ALERT_PHASE__LEN	1
+#define ALERT_PHASE__MSK	0x10
+#define ALERT_PHASE__REG	SMB380_STATUS_REG
+
+
+#define ST_RESULT__POS		7
+#define ST_RESULT__LEN		1
+#define ST_RESULT__MSK		0x80
+#define ST_RESULT__REG		SMB380_STATUS_REG
+
+
+/* CONTROL BITS */
+
+#define SLEEP__POS			0
+#define SLEEP__LEN			1
+#define SLEEP__MSK			0x01
+#define SLEEP__REG			SMB380_CTRL_REG
+
+#define SOFT_RESET__POS		1
+#define SOFT_RESET__LEN		1
+#define SOFT_RESET__MSK		0x02
+#define SOFT_RESET__REG		SMB380_CTRL_REG
+
+
+
+
+
+#define SELF_TEST__POS		2
+#define SELF_TEST__LEN		2
+#define SELF_TEST__MSK		0x0C
+#define SELF_TEST__REG		SMB380_CTRL_REG
+
+
+
+
+#define SELF_TEST0__POS		2
+#define SELF_TEST0__LEN		1
+#define SELF_TEST0__MSK		0x04
+#define SELF_TEST0__REG		SMB380_CTRL_REG
+
+#define SELF_TEST1__POS		3
+#define SELF_TEST1__LEN		1
+#define SELF_TEST1__MSK		0x08
+#define SELF_TEST1__REG		SMB380_CTRL_REG
+
+
+
+
+#define EE_W__POS			4
+#define EE_W__LEN			1
+#define EE_W__MSK			0x10
+#define EE_W__REG			SMB380_CTRL_REG
+
+#define UPDATE_IMAGE__POS	5
+#define UPDATE_IMAGE__LEN	1
+#define UPDATE_IMAGE__MSK	0x20
+#define UPDATE_IMAGE__REG	SMB380_CTRL_REG
+
+#define RESET_INT__POS		6
+#define RESET_INT__LEN		1
+#define RESET_INT__MSK		0x40
+#define RESET_INT__REG		SMB380_CTRL_REG
+
+
+
+/* LOW-G, HIGH-G settings */
+
+
+
+#define ENABLE_LG__POS		0
+#define ENABLE_LG__LEN		1
+#define ENABLE_LG__MSK		0x01
+#define ENABLE_LG__REG		SMB380_CONF1_REG
+
+
+
+
+#define ENABLE_HG__POS		1
+#define ENABLE_HG__LEN		1
+#define ENABLE_HG__MSK		0x02
+#define ENABLE_HG__REG		SMB380_CONF1_REG
+
+
+/* LG/HG counter */
+
+	
+
+#define COUNTER_LG__POS			2
+#define COUNTER_LG__LEN			2
+#define COUNTER_LG__MSK			0x0C
+#define COUNTER_LG__REG			SMB380_CONF1_REG
+	
+#define COUNTER_HG__POS			4
+#define COUNTER_HG__LEN			2
+#define COUNTER_HG__MSK			0x30
+#define COUNTER_HG__REG			SMB380_CONF1_REG
+
+
+
+
+/* LG/HG duration is in ms */
+
+#define LG_DUR__POS			0
+#define LG_DUR__LEN			8
+#define LG_DUR__MSK			0xFF
+#define LG_DUR__REG			LG_DURATION_REG
+
+#define HG_DUR__POS			0
+#define HG_DUR__LEN			8
+#define HG_DUR__MSK			0xFF
+#define HG_DUR__REG			HG_DURATION_REG
+
+
+
+
+				
+
+#define LG_THRES__POS		0
+#define LG_THRES__LEN		8
+#define LG_THRES__MSK		0xFF
+#define LG_THRES__REG		LG_THRESHOLD_REG
+
+
+
+
+
+#define HG_THRES__POS		0
+#define HG_THRES__LEN		8
+#define HG_THRES__MSK		0xFF
+#define HG_THRES__REG		HG_THRESHOLD_REG
+
+
+
+
+
+
+
+
+#define LG_HYST__POS			0
+#define LG_HYST__LEN			3
+#define LG_HYST__MSK			0x07
+#define LG_HYST__REG			HYSTERESIS_REG
+
+
+
+
+#define HG_HYST__POS			3
+#define HG_HYST__LEN			3
+#define HG_HYST__MSK			0x38
+#define HG_HYST__REG			HYSTERESIS_REG
+
+
+/* ANY MOTION and ALERT settings */
+
+#define EN_ANY_MOTION__POS		6
+#define EN_ANY_MOTION__LEN		1
+#define EN_ANY_MOTION__MSK		0x40
+#define EN_ANY_MOTION__REG		SMB380_CONF1_REG
+
+
+/* ALERT settings */
+
+
+#define ALERT__POS			7
+#define ALERT__LEN			1
+#define ALERT__MSK			0x80
+#define ALERT__REG			SMB380_CONF1_REG
+
+
+/* ANY MOTION Duration */
+
+
+
+
+#define ANY_MOTION_THRES__POS	0
+#define ANY_MOTION_THRES__LEN	8
+#define ANY_MOTION_THRES__MSK	0xFF
+#define ANY_MOTION_THRES__REG	MOTION_THRS_REG
+
+
+
+
+#define ANY_MOTION_DUR__POS		6
+#define ANY_MOTION_DUR__LEN		2
+#define ANY_MOTION_DUR__MSK		0xC0	
+#define ANY_MOTION_DUR__REG		HYSTERESIS_REG
+
+
+#define CUSTOMER_RESERVED1__POS		0
+#define CUSTOMER_RESERVED1__LEN	 	8
+#define CUSTOMER_RESERVED1__MSK		0xFF
+#define CUSTOMER_RESERVED1__REG		CUSTOMER1_REG
+
+#define CUSTOMER_RESERVED2__POS		0
+#define CUSTOMER_RESERVED2__LEN	 	8
+#define CUSTOMER_RESERVED2__MSK		0xFF
+#define CUSTOMER_RESERVED2__REG		CUSTOMER2_REG
+
+
+
+/* BANDWIDTH dependend definitions */
+
+#define BANDWIDTH__POS				0
+#define BANDWIDTH__LEN			 	3
+#define BANDWIDTH__MSK			 	0x07
+#define BANDWIDTH__REG				RANGE_BWIDTH_REG
+
+
+
+
+/* RANGE */
+
+#define RANGE__POS				3
+#define RANGE__LEN				2
+#define RANGE__MSK				0x18	
+#define RANGE__REG				RANGE_BWIDTH_REG
+
+
+/* WAKE UP */
+
+
+
+#define WAKE_UP__POS			0
+#define WAKE_UP__LEN			1
+#define WAKE_UP__MSK			0x01
+#define WAKE_UP__REG			SMB380_CONF2_REG
+
+
+
+
+#define WAKE_UP_PAUSE__POS		1
+#define WAKE_UP_PAUSE__LEN		2
+#define WAKE_UP_PAUSE__MSK		0x06
+#define WAKE_UP_PAUSE__REG		SMB380_CONF2_REG
+
+
+/* ACCELERATION DATA SHADOW */
+
+
+
+#define SHADOW_DIS__POS			3
+#define SHADOW_DIS__LEN			1
+#define SHADOW_DIS__MSK			0x08
+#define SHADOW_DIS__REG			SMB380_CONF2_REG
+
+
+/* LATCH Interrupt */
+
+
+
+#define LATCH_INT__POS			4
+#define LATCH_INT__LEN			1
+#define LATCH_INT__MSK			0x10
+#define LATCH_INT__REG			SMB380_CONF2_REG
+
+/* new data interrupt */
+
+
+#define NEW_DATA_INT__POS		5
+#define NEW_DATA_INT__LEN		1
+#define NEW_DATA_INT__MSK		0x20
+#define NEW_DATA_INT__REG		SMB380_CONF2_REG
+
+
+
+#define ENABLE_ADV_INT__POS		6
+#define ENABLE_ADV_INT__LEN		1
+#define ENABLE_ADV_INT__MSK		0x40
+#define ENABLE_ADV_INT__REG		SMB380_CONF2_REG
+
+
+#define SMB380_SPI4_OFF	0
+#define SMB380_SPI4_ON	1
+
+#define SPI4__POS				7
+#define SPI4__LEN				1
+#define SPI4__MSK				0x80
+#define SPI4__REG				SMB380_CONF2_REG
+
+
+#define OFFSET_X_LSB__POS	6
+#define OFFSET_X_LSB__LEN	2
+#define OFFSET_X_LSB__MSK	0xC0
+#define OFFSET_X_LSB__REG	OFFS_GAIN_X_REG
+
+#define GAIN_X__POS			0
+#define GAIN_X__LEN			6
+#define GAIN_X__MSK			0x3f
+#define GAIN_X__REG			OFFS_GAIN_X_REG
+
+
+#define OFFSET_Y_LSB__POS	6
+#define OFFSET_Y_LSB__LEN	2
+#define OFFSET_Y_LSB__MSK	0xC0
+#define OFFSET_Y_LSB__REG	OFFS_GAIN_Y_REG
+
+#define GAIN_Y__POS			0
+#define GAIN_Y__LEN			6
+#define GAIN_Y__MSK			0x3f
+#define GAIN_Y__REG			OFFS_GAIN_Y_REG
+
+
+#define OFFSET_Z_LSB__POS	6
+#define OFFSET_Z_LSB__LEN	2
+#define OFFSET_Z_LSB__MSK	0xC0
+#define OFFSET_Z_LSB__REG	OFFS_GAIN_Z_REG
+
+#define GAIN_Z__POS			0
+#define GAIN_Z__LEN			6
+#define GAIN_Z__MSK			0x3f
+#define GAIN_Z__REG			OFFS_GAIN_Z_REG
+
+#define OFFSET_T_LSB__POS	6
+#define OFFSET_T_LSB__LEN	2
+#define OFFSET_T_LSB__MSK	0xC0
+#define OFFSET_T_LSB__REG	OFFS_GAIN_T_REG
+
+#define GAIN_T__POS			0
+#define GAIN_T__LEN			6
+#define GAIN_T__MSK			0x3f
+#define GAIN_T__REG			OFFS_GAIN_T_REG
+
+#define OFFSET_X_MSB__POS	0
+#define OFFSET_X_MSB__LEN	8
+#define OFFSET_X_MSB__MSK	0xFF
+#define OFFSET_X_MSB__REG	OFFSET_X_REG
+
+
+#define OFFSET_Y_MSB__POS	0
+#define OFFSET_Y_MSB__LEN	8
+#define OFFSET_Y_MSB__MSK	0xFF
+#define OFFSET_Y_MSB__REG	OFFSET_Y_REG
+
+#define OFFSET_Z_MSB__POS	0
+#define OFFSET_Z_MSB__LEN	8
+#define OFFSET_Z_MSB__MSK	0xFF
+#define OFFSET_Z_MSB__REG	OFFSET_Z_REG
+
+#define OFFSET_T_MSB__POS	0
+#define OFFSET_T_MSB__LEN	8
+#define OFFSET_T_MSB__MSK	0xFF
+#define OFFSET_T_MSB__REG	OFFSET_T_REG
+
+
+
+
+
+#define SMB380_GET_BITSLICE(regvar, bitname)\
+			(regvar & bitname##__MSK) >> bitname##__POS
+
+
+#define SMB380_SET_BITSLICE(regvar, bitname, val)\
+		  (regvar & ~bitname##__MSK) | ((val<<bitname##__POS)&bitname##__MSK)  
+
+
+/** \endcond */
+
+
+/* CONSTANTS */
+
+
+/* range and bandwidth */
+
+#define SMB380_RANGE_2G			0 /**< sets range to 2G mode \see smb380_set_range() */
+#define SMB380_RANGE_4G			1 /**< sets range to 4G mode \see smb380_set_range() */
+#define SMB380_RANGE_8G			2 /**< sets range to 8G mode \see smb380_set_range() */
+
+
+#define SMB380_BW_25HZ		0	/**< sets bandwidth to 25HZ \see smb380_set_bandwidth() */
+#define SMB380_BW_50HZ		1	/**< sets bandwidth to 50HZ \see smb380_set_bandwidth() */
+#define SMB380_BW_100HZ		2	/**< sets bandwidth to 100HZ \see smb380_set_bandwidth() */
+#define SMB380_BW_190HZ		3	/**< sets bandwidth to 190HZ \see smb380_set_bandwidth() */
+#define SMB380_BW_375HZ		4	/**< sets bandwidth to 375HZ \see smb380_set_bandwidth() */
+#define SMB380_BW_750HZ		5	/**< sets bandwidth to 750HZ \see smb380_set_bandwidth() */
+#define SMB380_BW_1500HZ	6	/**< sets bandwidth to 1500HZ \see smb380_set_bandwidth() */
+
+/* mode settings */
+
+#define SMB380_MODE_NORMAL      0
+#define SMB380_MODE_SLEEP       2
+#define SMB380_MODE_WAKE_UP     3
+
+/* wake up */
+
+#define SMB380_WAKE_UP_PAUSE_20MS		0
+#define SMB380_WAKE_UP_PAUSE_80MS		1
+#define SMB380_WAKE_UP_PAUSE_320MS		2
+#define SMB380_WAKE_UP_PAUSE_2560MS		3
+
+
+/* LG/HG thresholds are in LSB and depend on RANGE setting */
+/* no range check on threshold calculation */
+
+#define SMB380_SELF_TEST0_ON		1
+#define SMB380_SELF_TEST1_ON		3
+
+#define SMB380_EE_W_OFF			0
+#define SMB380_EE_W_ON			1
+
+
+
+/* low-g, high-g, any_motion */
+
+
+#define SMB380_COUNTER_LG_RST		0
+#define SMB380_COUNTER_LG_0LSB		SMB380_COUNTER_LG_RST
+#define SMB380_COUNTER_LG_1LSB		1
+#define SMB380_COUNTER_LG_2LSB		2
+#define SMB380_COUNTER_LG_3LSB		3
+
+#define SMB380_COUNTER_HG_RST		0
+#define SMB380_COUNTER_HG_0LSB		SMB380_COUNTER_HG_RST
+#define SMB380_COUNTER_HG_1LSB		1
+#define SMB380_COUNTER_HG_2LSB		2
+#define SMB380_COUNTER_HG_3LSB		3
+
+#define SMB380_COUNTER_RST			0
+#define SMB380_COUNTER_0LSB			SMB380_COUNTER_RST
+#define SMB380_COUNTER_1LSB			1
+#define SMB380_COUNTER_2LSB			2
+#define SMB380_COUNTER_3LSB			3
+
+
+
+/** Macro to convert floating point low-g-thresholds in G to 8-bit register values.<br>
+  * Example: SMB380_LG_THRES_IN_G( 0.3, 2.0) generates the register value for 0.3G threshold in 2G mode.
+  * \brief convert g-values to 8-bit value
+ */
+#define SMB380_LG_THRES_IN_G( gthres, range)			((256 * gthres ) / range)
+
+/** Macro to convert floating point high-g-thresholds in G to 8-bit register values.<br>
+  * Example: SMB380_HG_THRES_IN_G( 1.4, 2.0) generates the register value for 1.4G threshold in 2G mode.
+  * \brief convert g-values to 8-bit value
+ */
+#define SMB380_HG_THRES_IN_G(gthres, range)				((256 * gthres ) / range)
+
+/** Macro to convert floating point low-g-hysteresis in G to 8-bit register values.<br>
+  * Example: SMB380_LG_HYST_THRES_IN_G( 0.2, 2.0) generates the register value for 0.2G threshold in 2G mode.
+  * \brief convert g-values to 8-bit value
+ */
+#define SMB380_LG_HYST_IN_G( ghyst, range )				((32 * ghyst) / range)
+
+/** Macro to convert floating point high-g-hysteresis in G to 8-bit register values.<br>
+  * Example: SMB380_HG_HYST_THRES_IN_G( 0.2, 2.0) generates the register value for 0.2G threshold in 2G mode.
+  * \brief convert g-values to 8-bit value
+ */
+#define SMB380_HG_HYST_IN_G( ghyst, range )				((32 * ghyst) / range)
+
+
+/** Macro to convert floating point G-thresholds to 8-bit register values<br>
+  * Example: SMB380_ANY_MOTION_THRES_IN_G( 1.2, 2.0) generates the register value for 1.2G threshold in 2G mode.
+  * \brief convert g-values to 8-bit value
+ */
+
+#define SMB380_ANY_MOTION_THRES_IN_G( gthres, range)	((128 * gthres ) / range)
+
+
+#define SMB380_ANY_MOTION_DUR_1		0
+#define SMB380_ANY_MOTION_DUR_3		1
+#define SMB380_ANY_MOTION_DUR_5		2
+#define SMB380_ANY_MOTION_DUR_7		3
+
+
+
+#define SMB380_SHADOW_DIS_OFF	0
+#define SMB380_SHADOW_DIS_ON	1
+
+#define SMB380_LATCH_INT_OFF	0
+#define SMB380_LATCH_INT_ON		1
+
+#define SMB380_NEW_DATA_INT_OFF	0
+#define SMB380_NEW_DATA_INT_ON	1
+
+#define SMB380_ENABLE_ADV_INT_OFF	0
+#define SMB380_ENABLE_ADV_INT_ON	1
+
+#define SMB380_EN_ANY_MOTION_OFF 	0
+#define SMB380_EN_ANY_MOTION_ON 	1
+
+
+#define SMB380_ALERT_OFF	0
+#define SMB380_ALERT_ON		1
+
+#define SMB380_ENABLE_LG_OFF	0
+#define SMB380_ENABLE_LG_ON		1
+
+#define SMB380_ENABLE_HG_OFF	0
+#define SMB380_ENABLE_HG_ON		1
+
+
+
+#define SMB380_INT_ALERT		(1<<7)
+#define SMB380_INT_ANY_MOTION	(1<<6)
+#define SMB380_INT_EN_ADV_INT	(1<<5)
+#define SMB380_INT_NEW_DATA		(1<<4)
+#define SMB380_INT_LATCH		(1<<3)
+#define SMB380_INT_HG			(1<<1)
+#define SMB380_INT_LG			(1<<0)
+
+
+#define SMB380_INT_STATUS_HG			(1<<0)
+#define SMB380_INT_STATUS_LG			(1<<1)
+#define SMB380_INT_STATUS_HG_LATCHED	(1<<2)
+#define SMB380_INT_STATUS_LG_LATCHED	(1<<3)
+#define SMB380_INT_STATUS_ALERT			(1<<4)
+#define SMB380_INT_STATUS_ST_RESULT		(1<<7)
+
+
+#define SMB380_CONF1_INT_MSK	((1<<ALERT__POS) | (1<<EN_ANY_MOTION__POS) | (1<<ENABLE_HG__POS) | (1<<ENABLE_LG__POS))
+#define SMB380_CONF2_INT_MSK	((1<<ENABLE_ADV_INT__POS) | (1<<NEW_DATA_INT__POS) | (1<<LATCH_INT__POS))
+
+
+
+
+
+
+
+
+
+/* Function prototypes */
+
+
+
+
+int smb380_init(smb380_t *);
+
+int smb380_set_image (smb380regs_t *);
+
+int smb380_get_image(smb380regs_t *);
+
+int smb380_get_offset(unsigned char, unsigned short *); 
+
+int smb380_set_offset(unsigned char, unsigned short ); 
+
+int smb380_set_offset_eeprom(unsigned char, unsigned short);
+
+int smb380_soft_reset(void); 
+
+int smb380_update_image(void); 
+
+int smb380_write_ee(unsigned char , unsigned char ) ;
+
+int smb380_set_ee_w(unsigned char);
+
+int smb380_selftest(unsigned char);
+
+int smb380_get_selftest_result(unsigned char *);
+
+int smb380_set_range(char); 
+
+int smb380_get_range(unsigned char*);
+
+int smb380_set_mode(unsigned char); 
+
+unsigned char smb380_get_mode(void);
+
+int smb380_set_wake_up_pause(unsigned char);
+
+int smb380_get_wake_up_pause(unsigned char *);
+
+int smb380_set_bandwidth(char);
+
+int smb380_get_bandwidth(unsigned char *);
+
+int smb380_set_low_g_threshold(unsigned char);
+
+int smb380_get_low_g_threshold(unsigned char*);
+
+int smb380_set_low_g_hysteresis(unsigned char);
+
+int smb380_set_low_g_countdown(unsigned char);
+
+int smb380_get_low_g_countdown(unsigned char *);
+
+int smb380_get_low_g_hysteresis(unsigned char*);
+
+int smb380_set_low_g_duration(unsigned char);
+
+int smb380_get_low_g_duration(unsigned char*);
+
+int smb380_set_high_g_threshold(unsigned char);
+
+int smb380_get_high_g_threshold(unsigned char*);
+
+int smb380_set_high_g_hysteresis(unsigned char);
+
+int smb380_set_high_g_countdown(unsigned char);
+
+int smb380_get_high_g_countdown(unsigned char *);
+
+int smb380_get_high_g_hysteresis(unsigned char*);
+
+int smb380_set_high_g_duration(unsigned char);
+
+int smb380_get_high_g_duration(unsigned char*);
+
+int smb380_set_any_motion_threshold(unsigned char);
+
+int smb380_get_any_motion_threshold(unsigned char*);
+
+int smb380_set_any_motion_count(unsigned char);
+
+int smb380_get_any_motion_count(unsigned char *);
+
+int smb380_read_accel_x(short *);
+
+int smb380_read_accel_y(short *);
+
+int smb380_read_accel_z(short *);
+
+int smb380_read_temperature(unsigned char*);
+
+int smb380_read_accel_xyz(smb380acc_t *);
+
+int smb380_get_interrupt_status(unsigned char *);
+
+int smb380_reset_interrupt(void);
+
+int smb380_set_interrupt_mask(unsigned char);
+
+int smb380_get_interrupt_mask(unsigned char *);
+
+int smb380_set_low_g_int(unsigned char);
+
+int smb380_set_high_g_int(unsigned char);
+
+int smb380_set_any_motion_int(unsigned char);
+
+int smb380_set_alert_int(unsigned char);
+
+int smb380_set_advanced_int(unsigned char);
+
+int smb380_latch_int(unsigned char);
+
+int smb380_set_new_data_int(unsigned char onoff);
+
+int smb380_pause(int);
+
+int smb380_read_reg(unsigned char , unsigned char *, unsigned char);
+
+int smb380_write_reg(unsigned char , unsigned char*, unsigned char );
+
+
+
+
+#endif   // __SMB380_H__
+
+
+
+
+
diff -urN android_2.6.29_org/drivers/mmc/host/Kconfig android_2.6.29/drivers/mmc/host/Kconfig
--- android_2.6.29_org/drivers/mmc/host/Kconfig	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/mmc/host/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -48,6 +48,18 @@
 
 	  If unsure, say N.
 
+config MMC_SDHCI_S3C
+        tristate "SDHCI support on Samsung S3C SoC"
+        depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
+        help
+          This selects the Secure Digital Host Controller Interface (SDHCI)
+          often referrered to as the HSMMC block in some of the Samsung S3C
+          range of SoC.
+
+          If you have a controller with this interface, say Y or M here.
+
+          If unsure, say N.
+
 config MMC_RICOH_MMC
 	tristate "Ricoh MMC Controller Disabler  (EXPERIMENTAL)"
 	depends on MMC_SDHCI_PCI
diff -urN android_2.6.29_org/drivers/mmc/host/Makefile android_2.6.29/drivers/mmc/host/Makefile
--- android_2.6.29_org/drivers/mmc/host/Makefile	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/mmc/host/Makefile	2009-04-10 11:13:25.000000000 +0900
@@ -12,6 +12,7 @@
 obj-$(CONFIG_MMC_MXC)		+= mxcmmc.o
 obj-$(CONFIG_MMC_SDHCI)		+= sdhci.o
 obj-$(CONFIG_MMC_SDHCI_PCI)	+= sdhci-pci.o
+obj-$(CONFIG_MMC_SDHCI_S3C)     += sdhci-s3c.o
 obj-$(CONFIG_MMC_RICOH_MMC)	+= ricoh_mmc.o
 obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
 obj-$(CONFIG_MMC_AU1X)		+= au1xmmc.o
diff -urN android_2.6.29_org/drivers/mmc/host/sdhci-s3c.c android_2.6.29/drivers/mmc/host/sdhci-s3c.c
--- android_2.6.29_org/drivers/mmc/host/sdhci-s3c.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/mmc/host/sdhci-s3c.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,375 @@
+/* linux/drivers/mmc/host/sdhci-s3c.c
+ *
+ * Copyright 2008 Openmoko Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * SDHCI (HSMMC) support for Samsung SoC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+#include "sdhci.h"
+
+#define MAX_BUS_CLK	(4)
+
+struct sdhci_s3c {
+	struct sdhci_host	*host;
+	struct platform_device	*pdev;
+	struct resource		*ioarea;
+	struct s3c_sdhci_platdata *pdata;
+	unsigned int		cur_clk;
+
+	struct clk		*clk_io;	/* clock for io bus */
+	struct clk		*clk_bus[MAX_BUS_CLK];
+};
+
+static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
+{
+	return sdhci_priv(host);
+}
+
+static u32 get_curclk(u32 ctrl2)
+{
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+	ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
+
+	return ctrl2;
+}
+
+static void sdhci_s3c_check_sclk(struct sdhci_host *host)
+{
+	struct sdhci_s3c *ourhost = to_s3c(host);
+	u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+
+	if (get_curclk(tmp) != ourhost->cur_clk) {
+		dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
+
+		tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+		tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
+		writel(tmp, host->ioaddr + 0x80);
+	}
+}
+
+static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
+{
+	struct sdhci_s3c *ourhost = to_s3c(host);
+	struct clk *busclk;
+	unsigned int rate, max;
+	int clk;
+
+	/* note, a reset will reset the clock source */
+
+	sdhci_s3c_check_sclk(host);
+
+	for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
+		busclk = ourhost->clk_bus[clk];
+		if (!busclk)
+			continue;
+
+		rate = clk_get_rate(busclk);
+		if (rate > max)
+			max = rate;
+	}
+
+	return max;
+}
+
+static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
+{
+	return sdhci_s3c_get_max_clk(host) / 1000000;
+}
+
+static void sdhci_s3c_set_ios(struct sdhci_host *host,
+			      struct mmc_ios *ios)
+{
+	struct sdhci_s3c *ourhost = to_s3c(host);
+	struct s3c_sdhci_platdata *pdata = ourhost->pdata;
+	int width;
+
+	sdhci_s3c_check_sclk(host);
+
+	if (ios->power_mode != MMC_POWER_OFF) {
+		switch (ios->bus_width) {
+		case MMC_BUS_WIDTH_4:
+			width = 4;
+			break;
+		case MMC_BUS_WIDTH_1:
+			width = 1;
+			break;
+		default:
+			BUG();
+		}
+
+		if (pdata->cfg_gpio)
+			pdata->cfg_gpio(ourhost->pdev, width);
+	}
+
+	if (pdata->cfg_card)
+		pdata->cfg_card(ourhost->pdev, host->ioaddr,
+				ios, host->mmc->card);
+}
+
+static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
+					     unsigned int src,
+					     unsigned int wanted)
+{
+	unsigned long rate;
+	struct clk *clksrc = ourhost->clk_bus[src];
+	int div;
+
+	if (!clksrc)
+		return UINT_MAX;
+
+	rate = clk_get_rate(clksrc);
+
+	for (div = 1; div < 256; div *= 2) {
+		if ((rate / div) <= wanted)
+			break;
+	}
+
+	dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
+		src, rate, wanted, rate / div);
+
+	return (wanted - (rate / div));
+}
+
+static void sdhci_s3c_change_clock(struct sdhci_host *host, unsigned int clock)
+{
+	struct sdhci_s3c *ourhost = to_s3c(host);
+	unsigned int best = UINT_MAX;
+	unsigned int delta;
+	int best_src = 0;
+	int src;
+	u32 ctrl;
+
+	for (src = 0; src < MAX_BUS_CLK; src++) {
+		delta = sdhci_s3c_consider_clock(ourhost, src, clock);
+		if (delta < best) {
+			best = delta;
+			best_src = src;
+		}
+	}
+
+	dev_dbg(&ourhost->pdev->dev,
+		"selected source %d, clock %d, delta %d\n",
+		 best_src, clock, best);
+
+	/* turn clock off to card before changing clock source */
+	writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+	/* select the new clock source */
+
+	if (ourhost->cur_clk != best_src) {
+		struct clk *clk = ourhost->clk_bus[best_src];
+
+		ourhost->cur_clk = best_src;
+		host->max_clk = clk_get_rate(clk);
+		host->timeout_clk = host->max_clk / 1000000;
+
+		ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+		ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+		ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
+		writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
+	}
+
+	sdhci_change_clock(host, clock);
+}
+
+static struct sdhci_ops sdhci_s3c_ops = {
+	.get_max_clock		= sdhci_s3c_get_max_clk,
+	.get_timeout_clock	= sdhci_s3c_get_timeout_clk,
+	.change_clock		= sdhci_s3c_change_clock,
+	.set_ios		= sdhci_s3c_set_ios,
+};
+
+static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
+{
+	struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
+	struct device *dev = &pdev->dev;
+	struct sdhci_host *host;
+	struct sdhci_s3c *sc;
+	struct resource *res;
+	int ret, irq, ptr, clks;
+
+	if (!pdata) {
+		dev_err(dev, "no device data specified\n");
+		return -ENOENT;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(dev, "no irq specified\n");
+		return irq;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "no memory specified\n");
+		return -ENOENT;
+	}
+
+	host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
+	if (IS_ERR(host)) {
+		dev_err(dev, "sdhci_alloc_host() failed\n");
+		return PTR_ERR(host);
+	}
+
+	sc = sdhci_priv(host);
+
+	sc->host = host;
+	sc->pdev = pdev;
+	sc->pdata = pdata;
+
+	sc->clk_io = clk_get(dev, "hsmmc");
+	if (IS_ERR(sc->clk_io)) {
+		dev_err(dev, "failed to get io clock\n");
+		ret = PTR_ERR(sc->clk_io);
+		goto err_io_clk;
+	}
+
+	/* enable the local io clock and keep it running for the moment. */
+	clk_enable(sc->clk_io);
+
+	for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
+		struct clk *clk;
+		char *name = pdata->clocks[ptr];
+
+		if (name == NULL)
+			continue;
+
+		clk = clk_get(dev, name);
+		if (IS_ERR(clk)) {
+			dev_err(dev, "failed to get clock %s\n", name);
+			continue;
+		}
+
+		clks++;
+		sc->clk_bus[ptr] = clk;
+		clk_enable(clk);
+
+		dev_info(dev, "clock source %d: %s (%ld Hz)\n",
+			 ptr, name, clk_get_rate(clk));
+	}
+
+	if (clks == 0) {
+		dev_err(dev, "failed to find any bus clocks\n");
+		ret = -ENOENT;
+		goto err_no_busclks;
+	}
+
+	sc->ioarea = request_mem_region(res->start, resource_size(res),
+					mmc_hostname(host->mmc));
+	if (!sc->ioarea) {
+		dev_err(dev, "failed to reserve register area\n");
+		ret = -ENXIO;
+		goto err_req_regs;
+	}
+
+	host->ioaddr = ioremap_nocache(res->start, resource_size(res));
+	if (!host->ioaddr) {
+		dev_err(dev, "failed to map registers\n");
+		ret = -ENXIO;
+		goto err_req_regs;
+	}
+
+	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdev, 0);
+
+	sdhci_s3c_check_sclk(host);
+
+	host->hw_name = "samsung-hsmmc";
+	host->ops = &sdhci_s3c_ops;
+	host->quirks = 0;
+	host->irq = irq;
+
+	/* Setup quirks for the controller */
+
+	/* Currently with ADMA enabled we are getting some length
+	 * interrupts that are not being dealt with, do disable
+	 * ADMA until this is sorted out. */
+	host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+	host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
+
+	/* It seems we do not get an DATA transfer complete on non-busy
+	 * transfers, not sure if this is a problem with this specific
+	 * SDHCI block, or a missing configuration that needs to be set. */
+	host->quirks |= SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY;
+
+	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
+			 SDHCI_QUIRK_32BIT_DMA_SIZE);
+
+	ret = sdhci_add_host(host);
+	if (ret) {
+		dev_err(dev, "sdhci_add_host() failed\n");
+		goto err_add_host;
+	}
+
+	return 0;
+
+ err_add_host:
+	release_resource(sc->ioarea);
+	kfree(sc->ioarea);
+
+ err_req_regs:
+	for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
+		clk_disable(sc->clk_bus[ptr]);
+		clk_put(sc->clk_bus[ptr]);
+	}
+
+ err_no_busclks:
+	clk_disable(sc->clk_io);
+	clk_put(sc->clk_io);
+
+ err_io_clk:
+	sdhci_free_host(host);
+
+	return ret;
+}
+
+static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver sdhci_s3c_driver = {
+	.probe		= sdhci_s3c_probe,
+	.remove		= __devexit_p(sdhci_s3c_remove),
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "s3c-sdhci",
+	},
+};
+
+static int __init sdhci_s3c_init(void)
+{
+	return platform_driver_register(&sdhci_s3c_driver);
+}
+
+static void __exit sdhci_s3c_exit(void)
+{
+	platform_driver_unregister(&sdhci_s3c_driver);
+}
+
+module_init(sdhci_s3c_init);
+module_exit(sdhci_s3c_exit);
+
+MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
+MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
+MODULE_LICENSE("GPLv2");
+MODULE_ALIAS("platform:s3c-sdhci");
diff -urN android_2.6.29_org/drivers/mmc/host/sdhci.c android_2.6.29/drivers/mmc/host/sdhci.c
--- android_2.6.29_org/drivers/mmc/host/sdhci.c	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/mmc/host/sdhci.c	2009-04-10 13:59:24.000000000 +0900
@@ -78,6 +78,11 @@
 		readl(host->ioaddr + SDHCI_CAPABILITIES),
 		readl(host->ioaddr + SDHCI_MAX_CURRENT));
 
+	if (host->flags & SDHCI_USE_ADMA)
+		printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
+		       readl(host->ioaddr + SDHCI_ADMA_ERROR),
+		       readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
+
 	printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 }
 
@@ -931,6 +936,11 @@
 	host->clock = clock;
 }
 
+void sdhci_change_clock(struct sdhci_host *host, unsigned int clock)
+{
+	sdhci_set_clock(host, clock);
+}
+
 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 {
 	u8 pwr;
@@ -1038,6 +1048,9 @@
 		sdhci_init(host);
 	}
 
+	if (host->ops->set_ios)
+		host->ops->set_ios(host, ios);
+
 	sdhci_set_clock(host, ios->clock);
 
 	if (ios->power_mode == MMC_POWER_OFF)
@@ -1288,14 +1301,24 @@
 	 *       controllers.
 	 */
 	if (host->cmd->flags & MMC_RSP_BUSY) {
+		u32 present;
+
 		if (host->cmd->data)
 			DBG("Cannot wait for busy signal when also "
 				"doing a data transfer");
-		else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
+		else if (!(host->quirks & SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY))
 			return;
 
-		/* The controller does not support the end-of-busy IRQ,
-		 * fall through and take the SDHCI_INT_RESPONSE */
+		/* The Samsung SDHCI does not seem to provide an INT_DATA_END
+		 * when the system goes non-busy, so check the state of the
+		 * transfer by reading SDHCI_PRESENT_STATE to see if the
+		 * controller is ready
+		 */
+
+		present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
+		DBG("busy? present %08x, intstat %08x\n", present, intmask);
+
+		/* fall through and take the SDHCI_INT_RESPONSE */
 	}
 
 	if (intmask & SDHCI_INT_RESPONSE)
@@ -1612,15 +1635,21 @@
 		mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
 	}
 
-	host->max_clk =
-		(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+	if (host->ops->get_max_clock)
+		host->max_clk = host->ops->get_max_clock(host);
+	else {
+		host->max_clk =	(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+		host->max_clk *= 1000000;
+	}
 	if (host->max_clk == 0) {
 		printk(KERN_ERR "%s: Hardware doesn't specify base clock "
 			"frequency.\n", mmc_hostname(mmc));
 		return -ENODEV;
 	}
-	host->max_clk *= 1000000;
 
+	if (host->ops->get_timeout_clock)
+		host->timeout_clk = host->ops->get_timeout_clock(host);
+	else
 	host->timeout_clk =
 		(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
 	if (host->timeout_clk == 0) {
diff -urN android_2.6.29_org/drivers/mmc/host/sdhci.h android_2.6.29/drivers/mmc/host/sdhci.h
--- android_2.6.29_org/drivers/mmc/host/sdhci.h	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/mmc/host/sdhci.h	2009-04-10 13:22:04.000000000 +0900
@@ -57,6 +57,7 @@
 #define  SDHCI_DATA_AVAILABLE	0x00000800
 #define  SDHCI_CARD_PRESENT	0x00010000
 #define  SDHCI_WRITE_PROTECT	0x00080000
+#define  SDHCI_DATA_BIT(x)	(1 << ((x) + 20))
 
 #define SDHCI_HOST_CONTROL 	0x28
 #define  SDHCI_CTRL_LED		0x01
@@ -210,6 +211,8 @@
 #define SDHCI_QUIRK_BROKEN_SMALL_PIO			(1<<13)
 /* Controller does not provide transfer-complete interrupt when not busy */
 #define SDHCI_QUIRK_NO_BUSY_IRQ				(1<<14)
+/* Controller does not provide transfer-complete interrupt when not busy */
+#define SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY		(1<<15)
 
 	int			irq;		/* Device IRQ */
 	void __iomem *		ioaddr;		/* Mapped address */
@@ -268,12 +271,21 @@
 
 struct sdhci_ops {
 	int		(*enable_dma)(struct sdhci_host *host);
+	unsigned int	(*get_max_clock)(struct sdhci_host *host);
+	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
+
+	void		(*change_clock)(struct sdhci_host *host,
+					unsigned int clock);
+
+	void		(*set_ios)(struct sdhci_host *host,
+				   struct mmc_ios *ios);
 };
 
 
 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 	size_t priv_size);
 extern void sdhci_free_host(struct sdhci_host *host);
+extern void sdhci_change_clock(struct sdhci_host *host, unsigned int clock);
 
 static inline void *sdhci_priv(struct sdhci_host *host)
 {
diff -urN android_2.6.29_org/drivers/mtd/nand/Kconfig android_2.6.29/drivers/mtd/nand/Kconfig
--- android_2.6.29_org/drivers/mtd/nand/Kconfig	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/mtd/nand/Kconfig	2009-04-10 11:13:53.000000000 +0900
@@ -180,6 +180,34 @@
 	  when the is NAND chip selected or released, but will save
 	  approximately 5mA of power when there is nothing happening.
 
+config MTD_NAND_S3C
+	tristate "NAND Flash support for S3C SoC"
+	depends on ARCH_S3C64XX && MTD_NAND
+	help
+	  This enables the NAND flash controller on the S3C.
+
+	  No board specfic support is done by this driver, each board
+	  must advertise a platform_device for the driver to attach.
+
+config MTD_NAND_S3C_DEBUG
+	bool "S3C NAND driver debug"
+	depends on MTD_NAND_S3C
+	help
+	  Enable debugging of the S3C NAND driver
+
+config MTD_NAND_S3C_HWECC
+	bool "S3C NAND Hardware ECC"
+	depends on MTD_NAND_S3C
+	help
+	  Enable the use of the S3C's internal ECC generator when
+	  using NAND. Early versions of the chip have had problems with
+	  incorrect ECC generation, and if using these, the default of
+	  software ECC is preferable.
+
+	  If you lay down a device with the hardware ECC, then you will
+	  currently not be able to switch to software, as there is no
+	  implementation for ECC method used by the S3C
+
 config MTD_NAND_DISKONCHIP
 	tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
 	depends on EXPERIMENTAL
diff -urN android_2.6.29_org/drivers/mtd/nand/Makefile android_2.6.29/drivers/mtd/nand/Makefile
--- android_2.6.29_org/drivers/mtd/nand/Makefile	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/mtd/nand/Makefile	2009-04-10 11:13:56.000000000 +0900
@@ -14,6 +14,7 @@
 obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
 obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB)	+= ppchameleonevb.o
 obj-$(CONFIG_MTD_NAND_S3C2410)		+= s3c2410.o
+obj-$(CONFIG_MTD_NAND_S3C)		+= s3c_nand.o
 obj-$(CONFIG_MTD_NAND_DISKONCHIP)	+= diskonchip.o
 obj-$(CONFIG_MTD_NAND_H1900)		+= h1910.o
 obj-$(CONFIG_MTD_NAND_RTC_FROM4)	+= rtc_from4.o
diff -urN android_2.6.29_org/drivers/mtd/nand/s3c_nand.c android_2.6.29/drivers/mtd/nand/s3c_nand.c
--- android_2.6.29_org/drivers/mtd/nand/s3c_nand.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/mtd/nand/s3c_nand.c	2009-04-10 12:35:46.000000000 +0900
@@ -0,0 +1,966 @@
+/* linux/drivers/mtd/nand/s3c_nand.c
+ *
+ * Copyright (c) 2007 Samsung Electronics
+ *
+ * Samsung S3C NAND driver
+ *
+ * $Id: s3c_nand.c,v 1.3 2008/11/19 10:07:24 jsgood Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Based on nand driver from Ben Dooks <ben@simtec.co.uk>
+ * modified by scsuh. based on au1550nd.c
+ *
+ * Many functions for hardware ecc are implemented by jsgood.
+ */
+
+/* Simple H/W Table for Implementation of S3C nand driver
+ * by scsuh
+ * ------------------------------------------------------------------
+ * |    En/Dis CE           |  required  |                          |
+ * |    En/Dis ALE          |      X     | * nand controller does   |
+ * |    En/Dis CLE          |      X     | * nand controller does   |
+ * |    Wait/Ready          |  required  |                          |
+ * |    Write Command       |  required  |                          |
+ * |    Write Address       |  required  |                          |
+ * |    Write Data          |  required  |                          |
+ * |    Read Data           |  required  |                          |
+ * |    WP on/off           |  required  | * board specific         |
+ * |    AP Specific Init    |  required  |                          |
+ * ------------------------------------------------------------------
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/jiffies.h>
+#include <linux/sched.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+
+#include <plat/regs-nand.h>
+#include <plat/nand.h>
+
+enum s3c_cpu_type {
+	TYPE_S3C2450,	/* including s3c2416 */
+	TYPE_S3C6400,
+	TYPE_S3C6410,	/* including s3c6430/31 */
+};
+
+struct s3c_nand_info {
+	/* mtd info */
+	struct nand_hw_control		controller;
+	struct s3c_nand_mtd_info	*mtds;
+	struct s3c2410_platform_nand	*platform;
+
+	/* device info */
+	struct device			*device;
+	struct resource			*area;
+	struct clk			*clk;
+	void __iomem			*regs;
+	void __iomem			*sel_reg;
+	int				sel_bit;
+	int				mtd_count;
+
+	enum s3c_cpu_type		cpu_type;
+};
+static struct s3c_nand_info s3c_nand;
+
+static struct mtd_info *s3c_mtd = NULL;
+
+/* Nand flash definition values by jsgood */
+#define S3C_NAND_TYPE_UNKNOWN	0x0
+#define S3C_NAND_TYPE_SLC	0x1
+#define S3C_NAND_TYPE_MLC	0x2
+
+/*
+ * Cached progamming disabled for now, Not sure if its worth the
+ * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
+ *
+ * if want to use cached program, define next
+ * by jsgood (modified to keep prevent rule)
+ */
+#undef	CONFIG_MTD_NAND_S3C_CACHEDPROG
+
+/* Nand flash global values by jsgood */
+int cur_ecc_mode = 0;
+int nand_type = S3C_NAND_TYPE_UNKNOWN;
+
+#if defined(CONFIG_MTD_NAND_S3C_HWECC)
+/* Nand flash oob definition for SLC 512b page size by jsgood */
+static struct nand_ecclayout s3c_nand_oob_16 = {
+	.eccbytes = 4,
+	.eccpos = {1, 2, 3, 4},
+	.oobfree = {
+		{.offset = 6,
+		 .length = 10}}
+};
+
+/* Nand flash oob definition for SLC 2k page size by jsgood */
+static struct nand_ecclayout s3c_nand_oob_64 = {
+	.eccbytes = 16,
+	.eccpos = {40, 41, 42, 43, 44, 45, 46, 47,
+		   48, 49, 50, 51, 52, 53, 54, 55},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 38}}
+};
+
+/* Nand flash oob definition for MLC 2k page size by jsgood */
+static struct nand_ecclayout s3c_nand_oob_mlc_64 = {
+	.eccbytes = 32,
+	.eccpos = {
+		   32, 33, 34, 35, 36, 37, 38, 39,
+		   40, 41, 42, 43, 44, 45, 46, 47,
+ 		   48, 49, 50, 51, 52, 53, 54, 55,
+   		   56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 28}}
+};
+#endif
+
+#if defined(CONFIG_MTD_NAND_S3C_DEBUG)
+/*
+ * Function to print out oob buffer for debugging
+ * Written by jsgood
+ */
+void print_oob(const char *header, struct mtd_info *mtd)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+
+	printk("%s:\t", header);
+
+	for(i = 0; i < 64; i++)
+		printk("%02x ", chip->oob_poi[i]);
+
+	printk("\n");
+}
+EXPORT_SYMBOL(print_oob);
+#endif
+
+
+/*
+ * Hardware specific access to control-lines function
+ * Written by jsgood
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+	unsigned int cur;
+	void __iomem *regs = s3c_nand.regs;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if (ctrl & NAND_NCE) {
+			if (dat != NAND_CMD_NONE) {
+				cur = readl(regs + S3C_NFCONT);
+				cur &= ~S3C_NFCONT_nFCE0;
+				writel(cur, regs + S3C_NFCONT);
+			}
+		} else {
+			cur = readl(regs + S3C_NFCONT);
+			cur |= S3C_NFCONT_nFCE0;
+			writel(cur, regs + S3C_NFCONT);
+		}
+	}
+
+	if (dat != NAND_CMD_NONE) {
+		if (ctrl & NAND_CLE)
+			writeb(dat, regs + S3C_NFCMMD);
+		else if (ctrl & NAND_ALE)
+			writeb(dat, regs + S3C_NFADDR);
+	}
+}
+
+/*
+ * Function for checking device ready pin
+ * Written by jsgood
+ */
+static int s3c_nand_device_ready(struct mtd_info *mtd)
+{
+	void __iomem *regs = s3c_nand.regs;
+/* it's to check the RnB nand signal bit and return to device ready condition in nand_base.c */
+	return ((readl(regs + S3C_NFSTAT) & S3C_NFSTAT_BUSY));
+}
+
+/*
+ * We don't use a bad block table
+ */
+static int s3c_nand_scan_bbt(struct mtd_info *mtdinfo)
+{
+	return 0;
+}
+
+#if defined(CONFIG_MTD_NAND_S3C_HWECC)
+#if 0
+/*
+ * S3C Nand flash chip enable function
+ * Written by jsgood
+ */
+static void s3c_nand_ce_on(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	chip->cmd_ctrl(mtd, 0x0, NAND_NCE | NAND_CTRL_CHANGE);
+	nand_wait_ready(mtd);
+}
+
+/*
+ * S3C Nand flash chip disable function
+ * Written by jsgood
+ */
+static void s3c_nand_ce_off(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_CTRL_CHANGE);
+	nand_wait_ready(mtd);
+}
+#endif
+
+/*
+ * Function for checking ECCEncDone in NFSTAT
+ * Written by jsgood
+ */
+static void s3c_nand_wait_enc(void)
+{
+        void __iomem *regs = s3c_nand.regs;
+        unsigned long timeo = jiffies;
+ 
+        timeo += 16;    /* when Hz=200,  jiffies interval 1/200=5mS, waiting for 80mS  80/5 = 16 */
+ 
+        /* Apply this short delay always to ensure that we do wait tWB in
+         * any case on any machine. */
+
+        while (time_before(jiffies, timeo)) {
+		if (readl(regs + S3C_NFSTAT) & S3C_NFSTAT_ECCENCDONE)
+				break;
+		cond_resched();
+	}
+}
+
+/*
+ * Function for checking ECCDecDone in NFSTAT
+ * Written by jsgood
+ */
+static void s3c_nand_wait_dec(void)
+{
+	void __iomem *regs = s3c_nand.regs;
+        unsigned long timeo = jiffies;
+ 
+        timeo += 16;    /* when Hz=200,  jiffies interval  1/200=5mS, waiting for 80mS  80/5 = 16 */
+ 
+        /* Apply this short delay always to ensure that we do wait tWB in
+         * any case on any machine. */
+
+        while (time_before(jiffies, timeo)) {
+		if (readl(regs + S3C_NFSTAT) & S3C_NFSTAT_ECCDECDONE)
+			break;
+		cond_resched();
+	}
+}
+
+/*
+ * Function for checking ECC Busy
+ * Written by jsgood
+ */
+static void s3c_nand_wait_ecc_busy(void)
+{
+	void __iomem *regs = s3c_nand.regs;
+        unsigned long timeo = jiffies;
+ 
+        timeo += 16;    /* when Hz=200,  jiffies interval  1/200=5mS, waiting for 80mS  80/5 = 16 */
+ 
+        /* Apply this short delay always to ensure that we do wait tWB in
+         * any case on any machine. */
+
+        while (time_before(jiffies, timeo)) {
+		if (!(readl(regs + S3C_NFMECCERR0) & S3C_NFECCERR0_ECCBUSY))
+			break;
+		cond_resched();
+	}
+}
+
+/*
+ * This function is called before encoding ecc codes to ready ecc engine.
+ * Written by jsgood
+ */
+static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	u_long nfcont;
+	u_long nfconf;
+	void __iomem *regs = s3c_nand.regs;
+
+	cur_ecc_mode = mode;
+
+	nfconf = readl(regs + S3C_NFCONF);
+
+	if (s3c_nand.cpu_type == TYPE_S3C6400) {
+		if (nand_type == S3C_NAND_TYPE_SLC)
+			nfconf &= ~S3C_NFCONF_ECC_MLC;	/* SLC */
+		else
+			nfconf |= S3C_NFCONF_ECC_MLC;	/* MLC */
+	} else {
+		nfconf &= ~(0x3 << 23);
+
+		if (nand_type == S3C_NAND_TYPE_SLC)
+			nfconf |= S3C_NFCONF_ECC_1BIT;
+		else
+			nfconf |= S3C_NFCONF_ECC_4BIT;
+	}
+
+	writel(nfconf, regs + S3C_NFCONF);
+
+	/* Init main ECC & unlock */
+	nfcont = readl(regs + S3C_NFCONT);
+	nfcont |= S3C_NFCONT_INITMECC;
+	nfcont &= ~S3C_NFCONT_MECCLOCK;
+
+	if (nand_type == S3C_NAND_TYPE_MLC) {
+		if (mode == NAND_ECC_WRITE)
+			nfcont |= S3C_NFCONT_ECC_ENC;
+		else if (mode == NAND_ECC_READ)
+			nfcont &= ~S3C_NFCONT_ECC_ENC;
+	}
+
+	writel(nfcont, regs + S3C_NFCONT);
+}
+
+/*
+ * This function is called immediately after encoding ecc codes.
+ * This function returns encoded ecc codes.
+ * Written by jsgood
+ */
+static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+{
+	u_long nfcont, nfmecc0, nfmecc1;
+	void __iomem *regs = s3c_nand.regs;
+
+	/* Lock */
+	nfcont = readl(regs + S3C_NFCONT);
+	nfcont |= S3C_NFCONT_MECCLOCK;
+	writel(nfcont, regs + S3C_NFCONT);
+
+	if (nand_type == S3C_NAND_TYPE_SLC) {
+		nfmecc0 = readl(regs + S3C_NFMECC0);
+
+		ecc_code[0] = nfmecc0 & 0xff;
+		ecc_code[1] = (nfmecc0 >> 8) & 0xff;
+		ecc_code[2] = (nfmecc0 >> 16) & 0xff;
+		ecc_code[3] = (nfmecc0 >> 24) & 0xff;
+	} else {
+		if (cur_ecc_mode == NAND_ECC_READ)
+			s3c_nand_wait_dec();
+		else {
+			s3c_nand_wait_enc();
+			
+			nfmecc0 = readl(regs + S3C_NFMECC0);
+			nfmecc1 = readl(regs + S3C_NFMECC1);
+
+			ecc_code[0] = nfmecc0 & 0xff;
+			ecc_code[1] = (nfmecc0 >> 8) & 0xff;
+			ecc_code[2] = (nfmecc0 >> 16) & 0xff;
+			ecc_code[3] = (nfmecc0 >> 24) & 0xff;			
+			ecc_code[4] = nfmecc1 & 0xff;
+			ecc_code[5] = (nfmecc1 >> 8) & 0xff;
+			ecc_code[6] = (nfmecc1 >> 16) & 0xff;
+			ecc_code[7] = (nfmecc1 >> 24) & 0xff;
+		}
+	}
+	
+	return 0;
+}
+
+/*
+ * This function determines whether read data is good or not.
+ * If SLC, must write ecc codes to controller before reading status bit.
+ * If MLC, status bit is already set, so only reading is needed.
+ * If status bit is good, return 0.
+ * If correctable errors occured, do that.
+ * If uncorrectable errors occured, return -1.
+ * Written by jsgood
+ */
+static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+{
+	int ret = -1;
+	u_long nfestat0, nfestat1, nfmeccdata0, nfmeccdata1, nfmlcbitpt;
+	u_char err_type;
+	void __iomem *regs = s3c_nand.regs;
+
+	if (!dat) {
+		printk("No page data\n");
+		return ret;
+	}
+
+	if (nand_type == S3C_NAND_TYPE_SLC) {
+		/* SLC: Write ECC data to compare */
+		nfmeccdata0 = (read_ecc[1] << 16) | read_ecc[0];
+		nfmeccdata1 = (read_ecc[3] << 16) | read_ecc[2];
+		writel(nfmeccdata0, regs + S3C_NFMECCDATA0);
+		writel(nfmeccdata1, regs + S3C_NFMECCDATA1);
+
+		/* Read ECC status */
+		nfestat0 = readl(regs + S3C_NFMECCERR0);
+		err_type = nfestat0 & 0x3;
+
+		switch (err_type) {
+		case 0: /* No error */
+			ret = 0;
+			break;
+
+		case 1: /* 1 bit error (Correctable)
+			   (nfestat0 >> 7) & 0x7ff	:error byte number
+			   (nfestat0 >> 4) & 0x7	:error bit number */
+			printk("s3c-nand: 1 bit error detected at byte %ld, correcting from "
+					"0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]);
+			dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7));
+			printk("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]);
+			ret = 1;
+			break;
+
+		case 2: /* Multiple error */
+		case 3: /* ECC area error */
+			printk("s3c-nand: ECC uncorrectable error detected\n");
+			ret = -1;
+			break;
+		}
+	} else {
+		/* MLC: */
+		s3c_nand_wait_ecc_busy();
+		
+		nfestat0 = readl(regs + S3C_NFMECCERR0);
+		nfestat1 = readl(regs + S3C_NFMECCERR1);
+		nfmlcbitpt = readl(regs + S3C_NFMLCBITPT);
+
+		err_type = (nfestat0 >> 26) & 0x7;
+
+		/* No error, If free page (all 0xff) */
+		if ((nfestat0 >> 29) & 0x1) {
+			err_type = 0;
+		} else {
+			/* No error, If all 0xff from 17th byte in oob (in case of JFFS2 format) */
+			if (dat) {
+				if (dat[17] == 0xff && dat[26] == 0xff && dat[35] == 0xff && dat[44] == 0xff && dat[54] == 0xff)
+					err_type = 0;
+			}
+		}
+
+		switch (err_type) {
+		case 5: /* Uncorrectable */
+			printk("s3c-nand: ECC uncorrectable error detected\n");
+			ret = -1;
+			break;
+
+		case 4: /* 4 bit error (Correctable) */
+			dat[(nfestat1 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 24) & 0xff);
+
+		case 3: /* 3 bit error (Correctable) */
+			dat[nfestat1 & 0x3ff] ^= ((nfmlcbitpt >> 16) & 0xff);
+
+		case 2: /* 2 bit error (Correctable) */
+			dat[(nfestat0 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 8) & 0xff);
+
+		case 1: /* 1 bit error (Correctable) */
+			printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);
+			dat[nfestat0 & 0x3ff] ^= (nfmlcbitpt & 0xff);
+			ret = err_type;
+			break;
+
+		case 0: /* No error */
+			ret = 0;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int s3c_nand_write_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+			      int page)
+{
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	int status = 0;
+	int eccbytes = chip->ecc.bytes;
+	int secc_start = mtd->oobsize - eccbytes;
+	int i;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+	/* spare area */
+	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+	chip->write_buf(mtd, chip->oob_poi, secc_start);
+	chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]);
+
+	for (i = 0; i < eccbytes; i++)
+		chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i];
+
+	chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+static int s3c_nand_read_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+			     int page, int sndcmd)
+{
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	int eccbytes = chip->ecc.bytes;
+	int secc_start = mtd->oobsize - eccbytes;
+	
+	if (sndcmd) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		sndcmd = 0;
+	}
+
+	chip->ecc.hwctl(mtd, NAND_ECC_READ);
+	chip->read_buf(mtd, chip->oob_poi, secc_start);
+	chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]);
+	chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+
+	/* jffs2 special case */
+	if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19))
+		chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0);
+	
+	return sndcmd;
+}
+
+static void s3c_nand_write_page_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+				  const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	int secc_start = mtd->oobsize - eccbytes;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	const uint8_t *p = buf;
+	
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+	/* main area */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+	}
+
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+	/* spare area */
+	chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+	chip->write_buf(mtd, chip->oob_poi, secc_start);
+	chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]);
+
+	for (i = 0; i < eccbytes; i++)
+		chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i];
+
+	chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+}
+
+static int s3c_nand_read_page_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf)
+{
+	int i, stat, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	int secc_start = mtd->oobsize - eccbytes;
+	int col = 0;
+	uint8_t *p = buf;	
+	uint32_t *mecc_pos = chip->ecc.layout->eccpos;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+
+	col = mtd->writesize;
+	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+
+	/* spare area */
+	chip->ecc.hwctl(mtd, NAND_ECC_READ);
+	chip->read_buf(mtd, chip->oob_poi, secc_start);
+	chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]);
+	chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+
+	/* jffs2 special case */
+	if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19))
+		chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0);
+
+	col = 0;
+
+	/* main area */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+		stat = chip->ecc.correct(mtd, p, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), 0);
+		if (stat == -1)
+			mtd->ecc_stats.failed++;
+
+		col = eccsize * (chip->ecc.steps + 1 - eccsteps);
+	}
+	
+	return 0;
+}
+
+/* 
+ * Hardware specific page read function for MLC.
+ * Written by jsgood
+ */
+static int s3c_nand_read_page_4bit(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf)
+{
+	int i, stat, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	int col = 0;
+	uint8_t *p = buf;	
+	uint32_t *mecc_pos = chip->ecc.layout->eccpos;
+
+	/* Step1: read whole oob */
+	col = mtd->writesize;
+	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	col = 0;
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->write_buf(mtd, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), eccbytes);
+		chip->ecc.calculate(mtd, 0, 0);
+		stat = chip->ecc.correct(mtd, p, 0, 0);
+
+		if (stat == -1)
+			mtd->ecc_stats.failed++;
+
+		col = eccsize * (chip->ecc.steps + 1 - eccsteps);
+	}
+
+	return 0;
+}
+
+/* 
+ * Hardware specific page write function for MLC.
+ * Written by jsgood
+ */
+static void s3c_nand_write_page_4bit(struct mtd_info *mtd, struct nand_chip *chip,
+				  const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	const uint8_t *p = buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint32_t *mecc_pos = chip->ecc.layout->eccpos;
+
+	/* Step1: write main data and encode mecc */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+	}
+
+	/* Step2: save encoded mecc */
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[mecc_pos[i]] = ecc_calc[i];
+
+	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+#endif
+
+/* s3c_nand_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code checks to see if
+ * it can allocate all necessary resources then calls the
+ * nand layer to look for devices
+ */
+static int s3c_nand_probe(struct platform_device *pdev, enum s3c_cpu_type cpu_type)
+{	
+	struct s3c_nand_mtd_info *plat_info = pdev->dev.platform_data;
+	struct mtd_partition *partition_info = (struct mtd_partition *)plat_info->partition;
+	struct nand_chip *nand;
+	struct resource *res;
+	int err = 0;
+	int ret = 0;
+	int i, j, size;
+
+#if defined(CONFIG_MTD_NAND_S3C_HWECC)
+	struct nand_flash_dev *type = NULL;
+	u_char tmp;
+#endif
+
+	/* get the clock source and enable it */
+	s3c_nand.clk = clk_get(&pdev->dev, "nand");
+	if (IS_ERR(s3c_nand.clk)) {
+		dev_err(&pdev->dev, "failed to get clock");
+		err = -ENOENT;
+		goto exit_error;
+	}
+
+	clk_enable(s3c_nand.clk);
+
+	/* allocate and map the resource */
+
+	/* currently we assume we have the one resource */
+	res  = pdev->resource;
+	size = res->end - res->start + 1;
+
+	s3c_nand.area = request_mem_region(res->start, size, pdev->name);
+
+	if (s3c_nand.area == NULL) {
+		dev_err(&pdev->dev, "cannot reserve register region\n");
+		err = -ENOENT;
+		goto exit_error;
+	}
+
+	s3c_nand.cpu_type   = cpu_type;
+	s3c_nand.device     = &pdev->dev;
+	s3c_nand.regs       = ioremap(res->start, size);
+
+	if (s3c_nand.regs == NULL) {
+		dev_err(&pdev->dev, "cannot reserve register region\n");
+		err = -EIO;
+		goto exit_error;
+	}
+
+	/* allocate memory for MTD device structure and private data */
+	s3c_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
+
+	if (!s3c_mtd) {
+		printk("Unable to allocate NAND MTD dev structure.\n");
+		return -ENOMEM;
+	}
+
+	/* Get pointer to private data */
+	nand = (struct nand_chip *) (&s3c_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *) s3c_mtd, 0, sizeof(struct mtd_info));
+	memset((char *) nand, 0, sizeof(struct nand_chip));
+
+	/* Link the private data with the MTD structure */
+	s3c_mtd->priv = nand;
+
+	for (i = 0; i < plat_info->chip_nr; i++) {
+		nand->IO_ADDR_R		= (char *)(s3c_nand.regs + S3C_NFDATA);
+		nand->IO_ADDR_W		= (char *)(s3c_nand.regs + S3C_NFDATA);
+		nand->cmd_ctrl		= s3c_nand_hwcontrol;
+		nand->dev_ready		= s3c_nand_device_ready;		
+		nand->scan_bbt		= s3c_nand_scan_bbt;
+		nand->options		= 0;
+
+#if defined(CONFIG_MTD_NAND_S3C_CACHEDPROG)
+		nand->options		|= NAND_CACHEPRG;
+#endif
+
+#if defined(CONFIG_MTD_NAND_S3C_HWECC)
+		nand->ecc.mode		= NAND_ECC_HW;
+		nand->ecc.hwctl		= s3c_nand_enable_hwecc;
+		nand->ecc.calculate	= s3c_nand_calculate_ecc;
+		nand->ecc.correct	= s3c_nand_correct_data;
+		
+		s3c_nand_hwcontrol(0, NAND_CMD_READID, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		s3c_nand_hwcontrol(0, 0x00, NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
+		s3c_nand_hwcontrol(0, 0x00, NAND_NCE | NAND_ALE);
+		s3c_nand_hwcontrol(0, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		s3c_nand_device_ready(0);
+
+		tmp = readb(nand->IO_ADDR_R); /* Maf. ID */
+		tmp = readb(nand->IO_ADDR_R); /* Device ID */
+
+		for (j = 0; nand_flash_ids[j].name != NULL; j++) {
+			if (tmp == nand_flash_ids[j].id) {
+				type = &nand_flash_ids[j];
+				break;
+			}
+		}
+
+		if (!type) {
+			printk("Unknown NAND Device.\n");
+			goto exit_error;
+		}
+		
+		nand->cellinfo = readb(nand->IO_ADDR_R);	/* the 3rd byte */
+		tmp = readb(nand->IO_ADDR_R);			/* the 4th byte */
+
+		if (!type->pagesize) {
+			if (((nand->cellinfo >> 2) & 0x3) == 0) {
+				nand_type = S3C_NAND_TYPE_SLC;				
+				nand->ecc.size = 512;
+				nand->ecc.bytes	= 4;
+
+				if ((1024 << (tmp & 0x3)) > 512) {
+					nand->ecc.read_page = s3c_nand_read_page_1bit;
+					nand->ecc.write_page = s3c_nand_write_page_1bit;
+					nand->ecc.read_oob = s3c_nand_read_oob_1bit;
+					nand->ecc.write_oob = s3c_nand_write_oob_1bit;
+					nand->ecc.layout = &s3c_nand_oob_64;
+				} else {
+					nand->ecc.layout = &s3c_nand_oob_16;
+				}
+			} else {
+				nand_type = S3C_NAND_TYPE_MLC;
+				nand->options |= NAND_NO_SUBPAGE_WRITE;	/* NOP = 1 if MLC */
+				nand->ecc.read_page = s3c_nand_read_page_4bit;
+				nand->ecc.write_page = s3c_nand_write_page_4bit;
+				nand->ecc.size = 512;
+				nand->ecc.bytes = 8;	/* really 7 bytes */
+				nand->ecc.layout = &s3c_nand_oob_mlc_64;
+			}
+		} else {
+			nand_type = S3C_NAND_TYPE_SLC;
+			nand->ecc.size = 512;
+			nand->cellinfo = 0;
+			nand->ecc.bytes = 4;
+			nand->ecc.layout = &s3c_nand_oob_16;
+		}
+
+		printk("S3C NAND Driver is using hardware ECC.\n");
+#else
+		nand->ecc.mode = NAND_ECC_SOFT;
+		printk("S3C NAND Driver is using software ECC.\n");
+#endif
+		if (nand_scan(s3c_mtd, 1)) {
+			ret = -ENXIO;
+			goto exit_error;
+		}
+
+		/* Register the partitions */
+		add_mtd_partitions(s3c_mtd, partition_info, plat_info->mtd_part_nr);
+	}
+
+	pr_debug("initialized ok\n");
+	return 0;
+
+exit_error:
+	kfree(s3c_mtd);
+
+	return ret;
+}
+
+static int s3c2450_nand_probe(struct platform_device *dev)
+{
+	return s3c_nand_probe(dev, TYPE_S3C2450);
+}
+
+static int s3c6400_nand_probe(struct platform_device *dev)
+{
+	return s3c_nand_probe(dev, TYPE_S3C6400);
+}
+
+static int s3c6410_nand_probe(struct platform_device *dev)
+{
+	return s3c_nand_probe(dev, TYPE_S3C6410);
+}
+
+/* PM Support */
+#if defined(CONFIG_PM)
+static int s3c_nand_suspend(struct platform_device *dev, pm_message_t pm)
+{
+	return 0;
+}
+
+static int s3c_nand_resume(struct platform_device *dev)
+{
+
+	return 0;
+}
+
+#else
+#define s3c_nand_suspend NULL
+#define s3c_nand_resume NULL
+#endif
+
+/* device management functions */
+static int s3c_nand_remove(struct platform_device *dev)
+{
+	platform_set_drvdata(dev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver s3c2450_nand_driver = {
+	.probe		= s3c2450_nand_probe,
+	.remove		= s3c_nand_remove,
+	.suspend	= s3c_nand_suspend,
+	.resume		= s3c_nand_resume,
+	.driver		= {
+		.name	= "s3c2450-nand",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static struct platform_driver s3c6400_nand_driver = {
+	.probe		= s3c6400_nand_probe,
+	.remove		= s3c_nand_remove,
+	.suspend	= s3c_nand_suspend,
+	.resume		= s3c_nand_resume,
+	.driver		= {
+		.name	= "s3c6400-nand",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static struct platform_driver s3c6410_nand_driver = {
+	.probe		= s3c6410_nand_probe,
+	.remove		= s3c_nand_remove,
+	.suspend	= s3c_nand_suspend,
+	.resume		= s3c_nand_resume,
+	.driver		= {
+		.name	= "s3c6410-nand",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init s3c_nand_init(void)
+{
+	printk("S3C NAND Driver, (c) 2008 Samsung Electronics\n");
+
+	platform_driver_register(&s3c2450_nand_driver);
+	platform_driver_register(&s3c6400_nand_driver);
+	return platform_driver_register(&s3c6410_nand_driver);
+}
+
+static void __exit s3c_nand_exit(void)
+{
+	platform_driver_unregister(&s3c2450_nand_driver);
+	platform_driver_unregister(&s3c6400_nand_driver);
+	platform_driver_unregister(&s3c6410_nand_driver);
+}
+
+module_init(s3c_nand_init);
+module_exit(s3c_nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
+MODULE_DESCRIPTION("S3C MTD NAND driver");
+
diff -urN android_2.6.29_org/drivers/net/Kconfig android_2.6.29/drivers/net/Kconfig
--- android_2.6.29_org/drivers/net/Kconfig	2009-04-20 13:34:53.000000000 +0900
+++ android_2.6.29/drivers/net/Kconfig	2009-04-16 20:03:02.000000000 +0900
@@ -981,10 +981,11 @@
 
 config SMSC911X
 	tristate "SMSC LAN911x/LAN921x families embedded ethernet support"
-	depends on ARM || SUPERH
+#	depends on ARM || SUPERH || MACH_SMDK6410
+	depends on MACH_SMDK6410
 	select CRC32
 	select MII
-	select PHYLIB
+#	select PHYLIB
 	---help---
 	  Say Y here if you want support for SMSC LAN911x and LAN921x families
 	  of ethernet controllers.
@@ -1419,7 +1420,7 @@
 config CS89x0
 	tristate "CS89x0 support"
 	depends on NET_ETHERNET && (ISA || EISA || MACH_IXDP2351 \
-		|| ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS)
+		|| ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS || MACH_SMDK6410)
 	---help---
 	  Support for CS89x0 chipset based Ethernet cards. If you have a
 	  network (Ethernet) card of this type, say Y and read the
@@ -1433,7 +1434,7 @@
 config CS89x0_NONISA_IRQ
 	def_bool y
 	depends on CS89x0 != n
-	depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS
+	depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS || MACH_SMDK6410
 
 config TC35815
 	tristate "TOSHIBA TC35815 Ethernet support"
diff -urN android_2.6.29_org/drivers/net/cs89x0.c android_2.6.29/drivers/net/cs89x0.c
--- android_2.6.29_org/drivers/net/cs89x0.c	2009-04-20 13:34:53.000000000 +0900
+++ android_2.6.29/drivers/net/cs89x0.c	2009-04-10 11:51:41.000000000 +0900
@@ -36,7 +36,7 @@
 
   Alan Cox          : Removed 1.2 support, added 2.1 extra counters.
 
-  Andrew Morton     : Kernel 2.3.48
+  Andrew Morton     : andrewm@uow.edu.au
                     : Handle kmalloc() failures
                     : Other resource allocation fixes
                     : Add SMP locks
@@ -48,7 +48,7 @@
                     : Fixed an out-of-mem bug in dma_rx()
                     : Updated Documentation/networking/cs89x0.txt
 
-  Andrew Morton     : Kernel 2.3.99-pre1
+  Andrew Morton     : andrewm@uow.edu.au / Kernel 2.3.99-pre1
                     : Use skb_reserve to longword align IP header (two places)
                     : Remove a delay loop from dma_rx()
                     : Replace '100' with HZ
@@ -56,11 +56,11 @@
                     : Added 'cs89x0_dma=N' kernel boot option
                     : Correctly initialise lp->lock in non-module compile
 
-  Andrew Morton     : Kernel 2.3.99-pre4-1
+  Andrew Morton     : andrewm@uow.edu.au / Kernel 2.3.99-pre4-1
                     : MOD_INC/DEC race fix (see
                     : http://www.uwsg.indiana.edu/hypermail/linux/kernel/0003.3/1532.html)
 
-  Andrew Morton     : Kernel 2.4.0-test7-pre2
+  Andrew Morton     : andrewm@uow.edu.au / Kernel 2.4.0-test7-pre2
                     : Enhanced EEPROM support to cover more devices,
                     :   abstracted IRQ mapping to support CONFIG_ARCH_CLPS7500 arch
                     :   (Jason Gunthorpe <jgg@ualberta.ca>)
@@ -144,6 +144,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <linux/irq.h>
 
 #include <asm/system.h>
 #include <asm/io.h>
@@ -170,7 +171,11 @@
 /* The cs8900 has 4 IRQ pins, software selectable. cs8900_irq_map maps
    them to system IRQ numbers. This mapping is card specific and is set to
    the configuration of the Cirrus Eval board for this chip. */
-#if defined(CONFIG_SH_HICOSH4)
+#ifdef CONFIG_ARCH_CLPS7500
+static unsigned int netcard_portlist[] __used __initdata =
+   { 0x80090303, 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
+static unsigned int cs8900_irq_map[] = {12,0,0,0};
+#elif defined(CONFIG_SH_HICOSH4)
 static unsigned int netcard_portlist[] __used __initdata =
    { 0x0300, 0};
 static unsigned int cs8900_irq_map[] = {1,0,0,0};
@@ -195,6 +200,12 @@
 	PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300, 0
 };
 static unsigned cs8900_irq_map[] = {EXPIO_INT_ENET_INT, 0, 0, 0};
+#elif defined(CONFIG_MACH_SMDK6410)
+#include <plat/map-base.h>
+#include <mach/map.h>
+//#define S3C64XX_VA_CS89X0	S3C_ADDR(0x30000000)
+static unsigned int netcard_portlist[] __initdata = {(uint)S3C64XX_VA_CS89X0 + 0x300, 0};
+static unsigned int cs8900_irq_map[] = {IRQ_EINT(11),0,0,0};
 #else
 static unsigned int netcard_portlist[] __used __initdata =
    { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
@@ -317,6 +328,12 @@
 	int irq;
 	int io;
 
+#if defined (CONFIG_MACH_SMDK6410)
+    if(unit > 0){
+        err = -ENODEV;
+        return ERR_PTR(err);
+    }
+#endif
 	if (!dev)
 		return ERR_PTR(-ENODEV);
 
@@ -517,6 +534,11 @@
 	unsigned rev_type = 0;
 	int eeprom_buff[CHKSUM_LEN];
 	int retval;
+	DECLARE_MAC_BUF(mac);
+
+#if defined(CONFIG_MACH_SMDK6410)	/* must fix this bug. scsuh */
+	set_irq_type(cs8900_irq_map[0], IRQ_TYPE_LEVEL_HIGH);
+#endif
 
 	/* Initialize the device structure. */
 	if (!modular) {
@@ -532,6 +554,10 @@
 #endif
 		lp->force = g_cs89x0_media__force;
 #endif
+
+#if defined(CONFIG_MACH_SMDK6410)
+		lp->force = FORCE_RJ45;
+#endif
         }
 
 #ifdef CONFIG_ARCH_PNX010X
@@ -802,7 +828,7 @@
 	} else {
 		i = lp->isa_config & INT_NO_MASK;
 		if (lp->chip_type == CS8900) {
-#ifdef CONFIG_CS89x0_NONISA_IRQ
+#ifdef CONFIG_MACH_SMDK6410
 		        i = cs8900_irq_map[0];
 #else
 			/* Translate the IRQ using the IRQ mapping table. */
@@ -839,9 +865,18 @@
 	{
 		printk(", programmed I/O");
 	}
+#if defined(CONFIG_MACH_SMDK6410)
+
+	dev->dev_addr[0] = 0x00;
+	dev->dev_addr[1] = 0x40;
+	dev->dev_addr[2] = 0x5c;
+	dev->dev_addr[3] = 0x26;
+	dev->dev_addr[4] = 0x0a;
+	dev->dev_addr[5] = 0x5b;
+#endif
 
 	/* print the ethernet address. */
-	printk(", MAC %pM", dev->dev_addr);
+	printk(", MAC %s", print_mac(mac, dev->dev_addr));
 
 	dev->open		= net_open;
 	dev->stop		= net_close;
@@ -1020,16 +1055,16 @@
 	}
         skb->protocol=eth_type_trans(skb,dev);
 	netif_rx(skb);
+	dev->last_rx = jiffies;
 	lp->stats.rx_packets++;
 	lp->stats.rx_bytes += length;
 }
 
 #endif	/* ALLOW_DMA */
 
-static void __init reset_chip(struct net_device *dev)
+void  __init reset_chip(struct net_device *dev)
 {
-#if !defined(CONFIG_MACH_MX31ADS)
-#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01)
+#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_MACH_SMDK6410)
 	struct net_local *lp = netdev_priv(dev);
 	int ioaddr = dev->base_addr;
 #endif
@@ -1040,7 +1075,7 @@
 	/* wait 30 ms */
 	msleep(30);
 
-#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01)
+#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_MACH_SMDK6410)
 	if (lp->chip_type != CS8900) {
 		/* Hardware problem requires PNP registers to be reconfigured after a reset */
 		writeword(ioaddr, ADD_PORT, PP_CS8920_ISAINT);
@@ -1057,7 +1092,6 @@
 	reset_start_time = jiffies;
 	while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2)
 		;
-#endif /* !CONFIG_MACH_MX31ADS */
 }
 
 
@@ -1306,6 +1340,7 @@
 #endif
 	{
 #ifndef CONFIG_CS89x0_NONISA_IRQ
+#if !defined(CONFIG_MACH_SMDK6410)
 		if (((1 << dev->irq) & lp->irq_map) == 0) {
 			printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n",
                                dev->name, dev->irq, lp->irq_map);
@@ -1313,6 +1348,7 @@
 			goto bad_out;
 		}
 #endif
+#endif
 /* FIXME: Cirrus' release had this: */
 		writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ );
 /* And 2.3.47 had this: */
@@ -1713,6 +1749,7 @@
 
         skb->protocol=eth_type_trans(skb,dev);
 	netif_rx(skb);
+	dev->last_rx = jiffies;
 	lp->stats.rx_packets++;
 	lp->stats.rx_bytes += length;
 }
@@ -1810,10 +1847,11 @@
 
 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 
-	if (net_debug)
-		printk("%s: Setting MAC address to %pM.\n",
-		       dev->name, dev->dev_addr);
-
+	if (net_debug) {
+		DECLARE_MAC_BUF(mac);
+		printk("%s: Setting MAC address to %s.\n",
+		       dev->name, print_mac(mac, dev->dev_addr));
+	}
 	/* set the Ethernet address */
 	for (i=0; i < ETH_ALEN/2; i++)
 		writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8));
diff -urN android_2.6.29_org/drivers/net/smsc911x.c android_2.6.29/drivers/net/smsc911x.c
--- android_2.6.29_org/drivers/net/smsc911x.c	2009-04-20 13:34:53.000000000 +0900
+++ android_2.6.29/drivers/net/smsc911x.c	2009-04-17 13:14:10.000000000 +0900
@@ -1203,7 +1203,6 @@
 	SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
 	pdata->software_irq_signal = 0;
 	smp_wmb();
-
 	temp = smsc911x_reg_read(pdata, INT_EN);
 	temp |= INT_EN_SW_INT_EN_;
 	smsc911x_reg_write(pdata, INT_EN, temp);
@@ -1904,6 +1903,10 @@
 
 	pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
 
+#if defined(CONFIG_MACH_SMDK6410)
+        set_irq_type(IRQ_EINT(11), IRQ_TYPE_LEVEL_LOW);
+#endif
+
 	/* platform data specifies irq & dynamic bus configuration */
 	if (!pdev->dev.platform_data) {
 		pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
diff -urN android_2.6.29_org/drivers/video/Kconfig android_2.6.29/drivers/video/Kconfig
--- android_2.6.29_org/drivers/video/Kconfig	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/video/Kconfig	2009-04-10 11:13:25.000000000 +0900
@@ -1920,6 +1920,30 @@
 	depends on FB_TMIO
 	default y
 
+config FB_S3C
+	tristate "Samsung S3C framebuffer support"
+	depends on FB && ARCH_S3C64XX
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	---help---
+	  Frame buffer driver for the built-in FB controller in the Samsung
+	  SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
+	  and the S3C64XX series such as the S3C6400 and S3C6410.
+
+	  These chips all have the same basic framebuffer design with the
+	  actual capabilities depending on the chip. For instance the S3C6400
+	  and S3C6410 support 4 hardware windows whereas the S3C24XX series
+	  currently only have two.
+
+	  Currently the support is only for the S3C6400 and S3C6410 SoCs.
+
+config FB_S3C_DEBUG_REGWRITE
+       bool "Debug register writes"
+       depends on FB_S3C
+       ---help---
+         Show all register writes via printk(KERN_DEBUG)
+
 config FB_S3C2410
 	tristate "S3C2410 LCD framebuffer support"
 	depends on FB && ARCH_S3C2410
diff -urN android_2.6.29_org/drivers/video/Makefile android_2.6.29/drivers/video/Makefile
--- android_2.6.29_org/drivers/video/Makefile	2009-04-20 13:34:52.000000000 +0900
+++ android_2.6.29/drivers/video/Makefile	2009-04-10 11:13:25.000000000 +0900
@@ -109,6 +109,7 @@
 obj-$(CONFIG_FB_S1D13XXX)	  += s1d13xxxfb.o
 obj-$(CONFIG_FB_SH7760)		  += sh7760fb.o
 obj-$(CONFIG_FB_IMX)              += imxfb.o
+obj-$(CONFIG_FB_S3C)		  += s3c-fb.o
 obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o
 obj-$(CONFIG_FB_FSL_DIU)	  += fsl-diu-fb.o
 obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
diff -urN android_2.6.29_org/drivers/video/s3c-fb.c android_2.6.29/drivers/video/s3c-fb.c
--- android_2.6.29_org/drivers/video/s3c-fb.c	1970-01-01 09:00:00.000000000 +0900
+++ android_2.6.29/drivers/video/s3c-fb.c	2009-04-10 11:13:25.000000000 +0900
@@ -0,0 +1,1041 @@
+/* linux/drivers/video/s3c-fb.c
+ *
+ * Copyright 2008 Openmoko Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung SoC Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/gfp.h>
+#include <linux/clk.h>
+#include <linux/fb.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <plat/fb.h>
+
+/* This driver will export a number of framebuffer interfaces depending
+ * on the configuration passed in via the platform data. Each fb instance
+ * maps to a hardware window. Currently there is no support for runtime
+ * setting of the alpha-blending functions that each window has, so only
+ * window 0 is actually useful.
+ *
+ * Window 0 is treated specially, it is used for the basis of the LCD
+ * output timings and as the control for the output power-down state.
+*/
+
+/* note, some of the functions that get called are derived from including
+ * <mach/regs-fb.h> as they are specific to the architecture that the code
+ * is being built for.
+*/
+
+#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
+#undef writel
+#define writel(v, r) do { \
+	printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
+	__raw_writel(v, r); } while(0)
+#endif /* FB_S3C_DEBUG_REGWRITE */
+
+struct s3c_fb;
+
+/**
+ * struct s3c_fb_win - per window private data for each framebuffer.
+ * @windata: The platform data supplied for the window configuration.
+ * @parent: The hardware that this window is part of.
+ * @fbinfo: Pointer pack to the framebuffer info for this window.
+ * @palette_buffer: Buffer/cache to hold palette entries.
+ * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
+ * @index: The window number of this window.
+ * @palette: The bitfields for changing r/g/b into a hardware palette entry.
+ */
+struct s3c_fb_win {
+	struct s3c_fb_pd_win	*windata;
+	struct s3c_fb		*parent;
+	struct fb_info		*fbinfo;
+	struct s3c_fb_palette	 palette;
+
+	u32			*palette_buffer;
+	u32			 pseudo_palette[16];
+	unsigned int		 index;
+};
+
+/**
+ * struct s3c_fb - overall hardware state of the hardware
+ * @dev: The device that we bound to, for printing, etc.
+ * @regs_res: The resource we claimed for the IO registers.
+ * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
+ * @regs: The mapped hardware registers.
+ * @enabled: A bitmask of enabled hardware windows.
+ * @pdata: The platform configuration data passed with the device.
+ * @windows: The hardware windows that have been claimed.
+ */
+struct s3c_fb {
+	struct device		*dev;
+	struct resource		*regs_res;
+	struct clk		*bus_clk;
+	void __iomem		*regs;
+
+	unsigned char		 enabled;
+
+	struct s3c_fb_platdata	*pdata;
+	struct s3c_fb_win	*windows[S3C_FB_MAX_WIN];
+};
+
+/**
+ * s3c_fb_win_has_palette() - determine if a mode has a palette
+ * @win: The window number being queried.
+ * @bpp: The number of bits per pixel to test.
+ *
+ * Work out if the given window supports palletised data at the specified bpp.
+ */
+static int s3c_fb_win_has_palette(unsigned int win, unsigned int bpp)
+{
+	return s3c_fb_win_pal_size(win) <= (1 << bpp);
+}
+
+/**
+ * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
+ * @var: The screen information to verify.
+ * @info: The framebuffer device.
+ *
+ * Framebuffer layer call to verify the given information and allow us to
+ * update various information depending on the hardware capabilities.
+ */
+static int s3c_fb_check_var(struct fb_var_screeninfo *var,
+			    struct fb_info *info)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb_pd_win *windata = win->windata;
+	struct s3c_fb *sfb = win->parent;
+
+	dev_dbg(sfb->dev, "checking parameters\n");
+
+	var->xres_virtual = max((unsigned int)windata->virtual_x, var->xres);
+	var->yres_virtual = max((unsigned int)windata->virtual_y, var->yres);
+
+	if (!s3c_fb_validate_win_bpp(win->index, var->bits_per_pixel)) {
+		dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
+			win->index, var->bits_per_pixel);
+		return -EINVAL;
+	}
+
+	/* always ensure these are zero, for drop through cases below */
+	var->transp.offset = 0;
+	var->transp.length = 0;
+
+	switch (var->bits_per_pixel) {
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		if (!s3c_fb_win_has_palette(win->index, var->bits_per_pixel)) {
+			/* non palletised, A:1,R:2,G:3,B:2 mode */
+			var->red.offset		= 4;
+			var->green.offset	= 2;
+			var->blue.offset	= 0;
+			var->red.length		= 5;
+			var->green.length	= 3;
+			var->blue.length	= 2;
+			var->transp.offset	= 7;
+			var->transp.length	= 1;
+		} else {
+			var->red.offset	= 0;
+			var->red.length	= var->bits_per_pixel;
+			var->green	= var->red;
+			var->blue	= var->red;
+		}
+		break;
+
+	case 19:
+		/* 666 with one bit alpha/transparency */
+		var->transp.offset	= 18;
+		var->transp.length	= 1;
+	case 18:
+		var->bits_per_pixel	= 32;
+
+		/* 666 format */
+		var->red.offset		= 12;
+		var->green.offset	= 6;
+		var->blue.offset	= 0;
+		var->red.length		= 6;
+		var->green.length	= 6;
+		var->blue.length	= 6;
+		break;
+
+	case 16:
+		/* 16 bpp, 565 format */
+		var->red.offset		= 11;
+		var->green.offset	= 5;
+		var->blue.offset	= 0;
+		var->red.length		= 5;
+		var->green.length	= 6;
+		var->blue.length	= 5;
+		break;
+
+	case 28:
+	case 25:
+		var->transp.length	= var->bits_per_pixel - 24;
+		var->transp.offset	= 24;
+		/* drop through */
+	case 24:
+		/* our 24bpp is unpacked, so 32bpp */
+		var->bits_per_pixel	= 32;
+	case 32:
+		var->red.offset		= 16;
+		var->red.length		= 8;
+		var->green.offset	= 8;
+		var->green.length	= 8;
+		var->blue.offset	= 0;
+		var->blue.length	= 8;
+		break;
+
+	default:
+		dev_err(sfb->dev, "invalid bpp\n");
+	}
+
+	dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
+	return 0;
+}
+
+/**
+ * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
+ * @sfb: The hardware state.
+ * @pixclock: The pixel clock wanted, in picoseconds.
+ *
+ * Given the specified pixel clock, work out the necessary divider to get
+ * close to the output frequency.
+ */
+static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
+{
+	unsigned long clk = clk_get_rate(sfb->bus_clk);
+	unsigned long long tmp;
+	unsigned int result;
+
+	tmp = (unsigned long long)clk;
+	tmp *= pixclk;
+
+	do_div(tmp, 1000000000UL);
+	result = (unsigned int)tmp / 1000;
+
+	dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
+		pixclk, clk, result, clk / result);
+
+	return result;
+}
+
+/**
+ * s3c_fb_align_word() - align pixel count to word boundary
+ * @bpp: The number of bits per pixel
+ * @pix: The value to be aligned.
+ *
+ * Align the given pixel count so that it will start on an 32bit word
+ * boundary.
+ */
+static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
+{
+	int pix_per_word;
+
+	if (bpp > 16)
+		return pix;
+
+	pix_per_word = (8 * 32) / bpp;
+	return ALIGN(pix, pix_per_word);
+}
+
+/**
+ * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
+ * @info: The framebuffer to change.
+ *
+ * Framebuffer layer request to set a new mode for the specified framebuffer
+ */
+static int s3c_fb_set_par(struct fb_info *info)
+{
+	struct fb_var_screeninfo *var = &info->var;
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	void __iomem *regs = sfb->regs;
+	int win_no = win->index;
+	u32 data;
+	u32 pagewidth;
+	int clkdiv;
+
+	dev_dbg(sfb->dev, "setting framebuffer parameters\n");
+
+	switch (var->bits_per_pixel) {
+	case 32:
+	case 24:
+	case 16:
+	case 12:
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
+		break;
+	case 8:
+		if (s3c_fb_win_has_palette(win_no, 8))
+			info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+		else
+			info->fix.visual = FB_VISUAL_TRUECOLOR;
+		break;
+	case 1:
+		info->fix.visual = FB_VISUAL_MONO01;
+		break;
+	default:
+		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+		break;
+	}
+
+	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
+
+	/* disable the window whilst we update it */
+	writel(0, regs + WINCON(win_no));
+
+	/* use window 0 as the basis for the lcd output timings */
+
+	if (win_no == 0) {
+		clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
+
+		data = sfb->pdata->vidcon0;
+		data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
+
+		if (clkdiv > 1)
+			data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
+		else
+			data &= ~VIDCON0_CLKDIR;	/* 1:1 clock */
+
+		/* write the timing data to the panel */
+
+		data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
+		writel(data, regs + VIDCON0);
+
+		data = VIDTCON0_VBPD(var->upper_margin - 1) |
+		       VIDTCON0_VFPD(var->lower_margin - 1) |
+		       VIDTCON0_VSPW(var->vsync_len - 1);
+
+		writel(data, regs + VIDTCON0);
+
+		data = VIDTCON1_HBPD(var->left_margin - 1) |
+		       VIDTCON1_HFPD(var->right_margin - 1) |
+		       VIDTCON1_HSPW(var->hsync_len - 1);
+
+		writel(data, regs + VIDTCON1);
+
+		data = VIDTCON2_LINEVAL(var->yres - 1) |
+		       VIDTCON2_HOZVAL(var->xres - 1);
+		writel(data, regs + VIDTCON2);
+	}
+
+	/* write the buffer address */
+
+	writel(info->fix.smem_start, regs + VIDW_BUF_START(win_no));
+
+	data = info->fix.smem_start + info->fix.line_length * var->yres;
+	writel(data, regs + VIDW_BUF_END(win_no));
+
+	pagewidth = (var->xres * var->bits_per_pixel) >> 3;
+	data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
+	       VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
+	writel(data, regs + VIDW_BUF_SIZE(win_no));
+
+	/* write 'OSD' registers to control position of framebuffer */
+
+	data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
+	writel(data, regs + VIDOSD_A(win_no));
+
+	data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
+						     var->xres - 1)) |
+	       VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
+
+	writel(data, regs + VIDOSD_B(win_no));
+
+	data = var->xres * var->yres;
+	if (s3c_fb_has_osd_d(win_no)) {
+		writel(data, regs + VIDOSD_D(win_no));
+		writel(0, regs + VIDOSD_C(win_no));
+	} else
+		writel(data, regs + VIDOSD_C(win_no));
+
+	data = WINCONx_ENWIN;
+
+	/* note, since we have to round up the bits-per-pixel, we end up
+	 * relying on the bitfield information for r/g/b/a to work out
+	 * exactly which mode of operation is intended. */
+
+	switch (var->bits_per_pixel) {
+	case 1:
+		data |= WINCON0_BPPMODE_1BPP;
+		data |= WINCONx_BITSWP;
+		data |= WINCONx_BURSTLEN_4WORD;
+		break;
+	case 2:
+		data |= WINCON0_BPPMODE_2BPP;
+		data |= WINCONx_BITSWP;
+		data |= WINCONx_BURSTLEN_8WORD;
+		break;
+	case 4:
+		data |= WINCON0_BPPMODE_4BPP;
+		data |= WINCONx_BITSWP;
+		data |= WINCONx_BURSTLEN_8WORD;
+		break;
+	case 8:
+		if (var->transp.length != 0)
+			data |= WINCON1_BPPMODE_8BPP_1232;
+		else
+			data |= WINCON0_BPPMODE_8BPP_PALETTE;
+		data |= WINCONx_BURSTLEN_8WORD;
+		data |= WINCONx_BYTSWP;
+		break;
+	case 16:
+		if (var->transp.length != 0)
+			data |= WINCON1_BPPMODE_16BPP_A1555;
+		else
+			data |= WINCON0_BPPMODE_16BPP_565;
+		data |= WINCONx_HAWSWP;
+		data |= WINCONx_BURSTLEN_16WORD;
+		break;
+	case 24:
+	case 32:
+		if (var->red.length == 6) {
+			if (var->transp.length != 0)
+				data |= WINCON1_BPPMODE_19BPP_A1666;
+			else
+				data |= WINCON1_BPPMODE_18BPP_666;
+		} else if (var->transp.length != 0)
+			data |= WINCON1_BPPMODE_25BPP_A1888;
+		else
+			data |= WINCON0_BPPMODE_24BPP_888;
+
+		data |= WINCONx_BURSTLEN_16WORD;
+		break;
+	}
+
+	writel(data, regs + WINCON(win_no));
+	writel(0x0, regs + WINxMAP(win_no));
+
+	return 0;
+}
+
+/**
+ * s3c_fb_update_palette() - set or schedule a palette update.
+ * @sfb: The hardware information.
+ * @win: The window being updated.
+ * @reg: The palette index being changed.
+ * @value: The computed palette value.
+ *
+ * Change the value of a palette register, either by directly writing to
+ * the palette (this requires the palette RAM to be disconnected from the
+ * hardware whilst this is in progress) or schedule the update for later.
+ *
+ * At the moment, since we have no VSYNC interrupt support, we simply set
+ * the palette entry directly.
+ */
+static void s3c_fb_update_palette(struct s3c_fb *sfb,
+				  struct s3c_fb_win *win,
+				  unsigned int reg,
+				  u32 value)
+{
+	void __iomem *palreg;
+	u32 palcon;
+
+	palreg = sfb->regs + s3c_fb_pal_reg(win->index, reg);
+
+	dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
+		__func__, win->index, reg, palreg, value);
+
+	win->palette_buffer[reg] = value;
+
+	palcon = readl(sfb->regs + WPALCON);
+	writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
+
+	if (s3c_fb_pal_is16(win->index))
+		writew(value, palreg);
+	else
+		writel(value, palreg);
+
+	writel(palcon, sfb->regs + WPALCON);
+}
+
+static inline unsigned int chan_to_field(unsigned int chan,
+					 struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+/**
+ * s3c_fb_setcolreg() - framebuffer layer request to change palette.
+ * @regno: The palette index to change.
+ * @red: The red field for the palette data.
+ * @green: The green field for the palette data.
+ * @blue: The blue field for the palette data.
+ * @trans: The transparency (alpha) field for the palette data.
+ * @info: The framebuffer being changed.
+ */
+static int s3c_fb_setcolreg(unsigned regno,
+			    unsigned red, unsigned green, unsigned blue,
+			    unsigned transp, struct fb_info *info)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	unsigned int val;
+
+	dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
+		__func__, win->index, regno, red, green, blue);
+
+	switch (info->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/* true-colour, use pseudo-palette */
+
+		if (regno < 16) {
+			u32 *pal = info->pseudo_palette;
+
+			val  = chan_to_field(red,   &info->var.red);
+			val |= chan_to_field(green, &info->var.green);
+			val |= chan_to_field(blue,  &info->var.blue);
+
+			pal[regno] = val;
+		}
+		break;
+
+	case FB_VISUAL_PSEUDOCOLOR:
+		if (regno < s3c_fb_win_pal_size(win->index)) {
+			val  = chan_to_field(red, &win->palette.r);
+			val |= chan_to_field(green, &win->palette.g);
+			val |= chan_to_field(blue, &win->palette.b);
+
+			s3c_fb_update_palette(sfb, win, regno, val);
+		}
+
+		break;
+
+	default:
+		return 1;	/* unknown type */
+	}
+
+	return 0;
+}
+
+/**
+ * s3c_fb_enable() - Set the state of the main LCD output
+ * @sfb: The main framebuffer state.
+ * @enable: The state to set.
+ */
+static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
+{
+	u32 vidcon0 = readl(sfb->regs + VIDCON0);
+
+	if (enable)
+		vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
+	else {
+		/* see the note in the framebuffer datasheet about
+		 * why you cannot take both of these bits down at the
+		 * same time. */
+
+		if (!(vidcon0 & VIDCON0_ENVID))
+			return;
+
+		vidcon0 |= VIDCON0_ENVID;
+		vidcon0 &= ~VIDCON0_ENVID_F;
+	}
+
+	writel(vidcon0, sfb->regs + VIDCON0);
+}
+
+/**
+ * s3c_fb_blank() - blank or unblank the given window
+ * @blank_mode: The blank state from FB_BLANK_*
+ * @info: The framebuffer to blank.
+ *
+ * Framebuffer layer request to change the power state.
+ */
+static int s3c_fb_blank(int blank_mode, struct fb_info *info)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	unsigned int index = win->index;
+	u32 wincon;
+
+	dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
+
+	wincon = readl(sfb->regs + WINCON(index));
+
+	switch (blank_mode) {
+	case FB_BLANK_POWERDOWN:
+		wincon &= ~WINCONx_ENWIN;
+		sfb->enabled &= ~(1 << index);
+		/* fall through to FB_BLANK_NORMAL */
+
+	case FB_BLANK_NORMAL:
+		/* disable the DMA and display 0x0 (black) */
+		writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
+		       sfb->regs + WINxMAP(index));
+		break;
+
+	case FB_BLANK_UNBLANK:
+		writel(0x0, sfb->regs + WINxMAP(index));
+		wincon |= WINCONx_ENWIN;
+		sfb->enabled |= (1 << index);
+		break;
+
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	default:
+		return 1;
+	}
+
+	writel(wincon, sfb->regs + WINCON(index));
+
+	/* Check the enabled state to see if we need to be running the
+	 * main LCD interface, as if there are no active windows then
+	 * it is highly likely that we also do not need to output
+	 * anything.
+	 */
+
+	/* We could do something like the following code, but the current
+	 * system of using framebuffer events means that we cannot make
+	 * the distinction between just window 0 being inactive and all
+	 * the windows being down.
+	 *
+	 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
+	*/
+
+	/* we're stuck with this until we can do something about overriding
+	 * the power control using the blanking event for a single fb.
+	 */
+	if (index == 0)
+		s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
+
+	return 0;
+}
+
+static struct fb_ops s3c_fb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_check_var	= s3c_fb_check_var,
+	.fb_set_par	= s3c_fb_set_par,
+	.fb_blank	= s3c_fb_blank,
+	.fb_setcolreg	= s3c_fb_setcolreg,
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+};
+
+/**
+ * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
+ * @sfb: The base resources for the hardware.
+ * @win: The window to initialise memory for.
+ *
+ * Allocate memory for the given framebuffer.
+ */
+static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
+					 struct s3c_fb_win *win)
+{
+	struct s3c_fb_pd_win *windata = win->windata;
+	unsigned int real_size, virt_size, size;
+	struct fb_info *fbi = win->fbinfo;
+	dma_addr_t map_dma;
+
+	dev_dbg(sfb->dev, "allocating memory for display\n");
+
+	real_size = windata->win_mode.xres * windata->win_mode.yres;
+	virt_size = windata->virtual_x * windata->virtual_y;
+
+	dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
+		real_size, windata->win_mode.xres, windata->win_mode.yres,
+		virt_size, windata->virtual_x, windata->virtual_y);
+
+	size = (real_size > virt_size) ? real_size : virt_size;
+	size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
+	size /= 8;
+
+	fbi->fix.smem_len = size;
+	size = PAGE_ALIGN(size);
+
+	dev_dbg(sfb->dev, "want %u bytes for window\n", size);
+
+	fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
+						  &map_dma, GFP_KERNEL);
+	if (!fbi->screen_base)
+		return -ENOMEM;
+
+	dev_dbg(sfb->dev, "mapped %x to %p\n",
+		(unsigned int)map_dma, fbi->screen_base);
+
+	memset(fbi->screen_base, 0x0, size);
+	fbi->fix.smem_start = map_dma;
+
+	return 0;
+}
+
+/**
+ * s3c_fb_free_memory() - free the display memory for the given window
+ * @sfb: The base resources for the hardware.
+ * @win: The window to free the display memory for.
+ *
+ * Free the display memory allocated by s3c_fb_alloc_memory().
+ */
+static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
+{
+	struct fb_info *fbi = win->fbinfo;
+
+	dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
+			      fbi->screen_base, fbi->fix.smem_start);
+}
+
+/**
+ * s3c_fb_release_win() - release resources for a framebuffer window.
+ * @win: The window to cleanup the resources for.
+ *
+ * Release the resources that where claimed for the hardware window,
+ * such as the framebuffer instance and any memory claimed for it.
+ */
+static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
+{
+	fb_dealloc_cmap(&win->fbinfo->cmap);
+	unregister_framebuffer(win->fbinfo);
+	s3c_fb_free_memory(sfb, win);
+}
+
+/**
+ * s3c_fb_probe_win() - register an hardware window
+ * @sfb: The base resources for the hardware
+ * @res: Pointer to where to place the resultant window.
+ *
+ * Allocate and do the basic initialisation for one of the hardware's graphics
+ * windows.
+ */
+static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
+				      struct s3c_fb_win **res)
+{
+	struct fb_var_screeninfo *var;
+	struct fb_videomode *initmode;
+	struct s3c_fb_pd_win *windata;
+	struct s3c_fb_win *win;
+	struct fb_info *fbinfo;
+	int palette_size;
+	int ret;
+
+	dev_dbg(sfb->dev, "probing window %d\n", win_no);
+
+	palette_size = s3c_fb_win_pal_size(win_no);
+
+	fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
+				   palette_size * sizeof(u32), sfb->dev);
+	if (!fbinfo) {
+		dev_err(sfb->dev, "failed to allocate framebuffer\n");
+		return -ENOENT;
+	}
+
+	windata = sfb->pdata->win[win_no];
+	initmode = &windata->win_mode;
+
+	WARN_ON(windata->max_bpp == 0);
+	WARN_ON(windata->win_mode.xres == 0);
+	WARN_ON(windata->win_mode.yres == 0);
+
+	win = fbinfo->par;
+	var = &fbinfo->var;
+	win->fbinfo = fbinfo;
+	win->parent = sfb;
+	win->windata = windata;
+	win->index = win_no;
+	win->palette_buffer = (u32 *)(win + 1);
+
+	ret = s3c_fb_alloc_memory(sfb, win);
+	if (ret) {
+		dev_err(sfb->dev, "failed to allocate display memory\n");
+		goto err_framebuffer;
+	}
+
+	/* setup the r/b/g positions for the window's palette */
+	s3c_fb_init_palette(win_no, &win->palette);
+
+	/* setup the initial video mode from the window */
+	fb_videomode_to_var(&fbinfo->var, initmode);
+
+	fbinfo->fix.type	= FB_TYPE_PACKED_PIXELS;
+	fbinfo->fix.accel	= FB_ACCEL_NONE;
+	fbinfo->var.activate	= FB_ACTIVATE_NOW;
+	fbinfo->var.vmode	= FB_VMODE_NONINTERLACED;
+	fbinfo->var.bits_per_pixel = windata->default_bpp;
+	fbinfo->fbops		= &s3c_fb_ops;
+	fbinfo->flags		= FBINFO_FLAG_DEFAULT;
+	fbinfo->pseudo_palette  = &win->pseudo_palette;
+
+	/* prepare to actually start the framebuffer */
+
+	ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
+	if (ret < 0) {
+		dev_err(sfb->dev, "check_var failed on initial video params\n");
+		goto err_alloc_mem;
+	}
+
+	/* create initial colour map */
+
+	ret = fb_alloc_cmap(&fbinfo->cmap, s3c_fb_win_pal_size(win_no), 1);
+	if (ret == 0)
+		fb_set_cmap(&fbinfo->cmap, fbinfo);
+	else
+		dev_err(sfb->dev, "failed to allocate fb cmap\n");
+
+	s3c_fb_set_par(fbinfo);
+
+	dev_dbg(sfb->dev, "about to register framebuffer\n");
+
+	/* run the check_var and set_par on our configuration. */
+
+	ret = register_framebuffer(fbinfo);
+	if (ret < 0) {
+		dev_err(sfb->dev, "failed to register framebuffer\n");
+		goto err_alloc_mem;
+	}
+
+	*res = win;
+	dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
+
+	return 0;
+
+err_alloc_mem:
+	s3c_fb_free_memory(sfb, win);
+
+err_framebuffer:
+	unregister_framebuffer(fbinfo);
+	return ret;
+}
+
+/**
+ * s3c_fb_clear_win() - clear hardware window registers.
+ * @sfb: The base resources for the hardware.
+ * @win: The window to process.
+ *
+ * Reset the specific window registers to a known state.
+ */
+static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
+{
+	void __iomem *regs = sfb->regs;
+
+	writel(0, regs + WINCON(win));
+	writel(0xffffff, regs + WxKEYCONy(win, 0));
+	writel(0xffffff, regs + WxKEYCONy(win, 1));
+
+	writel(0, regs + VIDOSD_A(win));
+	writel(0, regs + VIDOSD_B(win));
+	writel(0, regs + VIDOSD_C(win));
+}
+
+static int __devinit s3c_fb_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct s3c_fb_platdata *pd;
+	struct s3c_fb *sfb;
+	struct resource *res;
+	int win;
+	int ret = 0;
+
+	dev_dbg(dev, "Entered %s\n", __FUNCTION__);
+
+	pd = pdev->dev.platform_data;
+	if (!pd) {
+		dev_err(dev, "no platform data specified\n");
+		return -EINVAL;
+	}
+
+	sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
+	if (!sfb) {
+		dev_err(dev, "no memory for framebuffers\n");
+		return -ENOMEM;
+	}
+
+	sfb->dev = dev;
+	sfb->pdata = pd;
+
+	sfb->bus_clk = clk_get(dev, "lcd");
+	if (IS_ERR(sfb->bus_clk)) {
+		dev_err(dev, "failed to get bus clock\n");
+		goto err_sfb;
+	}
+
+	clk_enable(sfb->bus_clk);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "failed to find registers\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+	sfb->regs_res = request_mem_region(res->start, resource_size(res),
+					   dev_name(dev));
+	if (!sfb->regs_res) {
+		dev_err(dev, "failed to claim register region\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+	sfb->regs = ioremap(res->start, resource_size(res));
+	if (!sfb->regs) {
+		dev_err(dev, "failed to map registers\n");
+		ret = -ENXIO;
+		goto err_req_region;
+	}
+
+	dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
+
+	/* setup gpio and output polarity controls */
+
+	pd->setup_gpio();
+
+	writel(pd->vidcon1, sfb->regs + VIDCON1);
+
+	/* zero all windows before we do anything */
+
+	for (win = 0; win < S3C_FB_MAX_WIN; win++)
+		s3c_fb_clear_win(sfb, win);
+
+	/* we have the register setup, start allocating framebuffers */
+
+	for (win = 0; win < S3C_FB_MAX_WIN; win++) {
+		if (!pd->win[win])
+			continue;
+
+		ret = s3c_fb_probe_win(sfb, win, &sfb->windows[win]);
+		if (ret < 0) {
+			dev_err(dev, "failed to create window %d\n", win);
+			for (; win >= 0; win--)
+				s3c_fb_release_win(sfb, sfb->windows[win]);
+			goto err_ioremap;
+		}
+	}
+
+	platform_set_drvdata(pdev, sfb);
+
+	dev_dbg(dev, "Exited %s\n", __FUNCTION__);
+
+	return 0;
+
+err_ioremap:
+	iounmap(sfb->regs);
+
+err_req_region:
+	release_resource(sfb->regs_res);
+	kfree(sfb->regs_res);
+
+err_clk:
+	clk_disable(sfb->bus_clk);
+	clk_put(sfb->bus_clk);
+
+err_sfb:
+	kfree(sfb);
+	return ret;
+}
+
+/**
+ * s3c_fb_remove() - Cleanup on module finalisation
+ * @pdev: The platform device we are bound to.
+ *
+ * Shutdown and then release all the resources that the driver allocated
+ * on initialisation.
+ */
+static int __devexit s3c_fb_remove(struct platform_device *pdev)
+{
+	struct s3c_fb *sfb = platform_get_drvdata(pdev);
+	int win;
+
+	for (win = 0; win <= S3C_FB_MAX_WIN; win++)
+		s3c_fb_release_win(sfb, sfb->windows[win]);
+
+	iounmap(sfb->regs);
+
+	clk_disable(sfb->bus_clk);
+	clk_put(sfb->bus_clk);
+
+	release_resource(sfb->regs_res);
+	kfree(sfb->regs_res);
+
+	kfree(sfb);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct s3c_fb *sfb = platform_get_drvdata(pdev);
+	struct s3c_fb_win *win;
+	int win_no;
+
+	for (win_no = S3C_FB_MAX_WIN; win_no >= 0; win_no--) {
+		win = sfb->windows[win_no];
+		if (!win)
+			continue;
+
+		/* use the blank function to push into power-down */
+		s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
+	}
+
+	clk_disable(sfb->bus_clk);
+	return 0;
+}
+
+static int s3c_fb_resume(struct platform_device *pdev)
+{
+	struct s3c_fb *sfb = platform_get_